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UPD703103A Datasheet(PDF) 73 Page - NEC

No. de Pieza. UPD703103A
Descripción  32-Bit Single-Chip Microcontrollers
Descarga  99 Pages
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Fabricante  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD703103A Datasheet(HTML) 73 Page - NEC

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CHAPTER 5 APPLICATION EXAMPLES
Application Note U17121EJ1V1AN
73
5.5.3 V850E/ME2 PCI host bridge macro initialization sample program list
/////////////////////////////////////////////////////////////////
//
V850E/ME2 - PCI Host Bridge Macro initialization sample
//
//
Overview: Initializes PCI Host Bridge Macro by setting
//
//
PCI Bridge IO area register group.
//
//
Specific initialization is described in
//
//
function PCI_HBM_Init().
//
//
//
//
PCI_HBM_Init() is called after functions required for
//
//
accessing Host Bridge Macro, such as CPU and peripheral
//
//
I/O, are initialized.
//
//
//
/////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
//
Defines base address of PCI area and SDRAM area.
//
//
Start address of PCI area is 0C80_0000H, and start address //
//
of SDRAM area is 0400_0000H in this application.
//
/////////////////////////////////////////////////////////////////
#define BASE_ADDRESS_ME2PCIIF
(0x0C800000)
#define BASE_ADDRESS_PCI_IO
(BASE_ADDRESS_ME2PCIIF)
#define BASE_ADDRESS_PCI_BRIDGE_IO
(BASE_ADDRESS_ME2PCIIF + 0x00200000)
#define BASE_ADDRESS_PCI_MEM
(BASE_ADDRESS_ME2PCIIF + 0x00400000)
#define BASE_ADDRESS_SDRAM
(0x04000000)
#define RANGE_SDRAM
(0x03FFFFFF)
// 64MB
////////////////////////////////////////////////////////
//
PCI Host Bridge Macro register address definition //
////////////////////////////////////////////////////////
#define PHBMR_PCI_CONFIG_DATA
(BASE_ADDRESS_PCI_BRIDGE_IO+0x00)
#define PHBMR_PCI_CONFIG_ADD
(BASE_ADDRESS_PCI_BRIDGE_IO+0x04)
#define PHBMR_PCI_CONTROL
(BASE_ADDRESS_PCI_BRIDGE_IO+0x08)
#define PHBMR_PCI_IO_BASE
(BASE_ADDRESS_PCI_BRIDGE_IO+0x10)
#define PHBMR_PCI_MEM_BASE
(BASE_ADDRESS_PCI_BRIDGE_IO+0x14)
#define PHBMR_PCI_INT_CTL
(BASE_ADDRESS_PCI_BRIDGE_IO+0x18)
#define PHBMR_PCI_ERR_ADD
(BASE_ADDRESS_PCI_BRIDGE_IO+0x1C)
#define PHBMR_SYSTEM_MEM_BASE
(BASE_ADDRESS_PCI_BRIDGE_IO+0x40)
#define PHBMR_SYSTEM_MEM_RANGE
(BASE_ADDRESS_PCI_BRIDGE_IO+0x44)
#define PHBMR_SDRAM_CTL
(BASE_ADDRESS_PCI_BRIDGE_IO+0x48)
///////////////////////////////////////////
//
Macro definition for register access //
///////////////////////////////////////////
#define V850EME2_REGW(x)
*((volatile unsigned int *)((int)x))


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