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UPD703108 Datasheet(PDF) 40 Page - NEC |
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UPD703108 Datasheet(HTML) 40 Page - NEC |
40 / 99 page CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO Application Note U17121EJ1V1AN 40 3.4.7 PCI_ERR_ADD register The PCI_ERR_ADD register retains the PCI bus address when the following errors occur. • System error (SERR# reception) • Parity error (PERR# reception) • Master abort • Target abort When the PCI_ERR_ADD register is read, all the bits are cleared. Once an error occurs and a value is set to the PCI_ERR_ADD register, the first value is retained until read access is performed or a new error occurs and the value is updated. This function is used only for debugging and is not used in normal operation. After reset: 00000000H R Offset address: 1CH 31 0 ERR_ADR Bit Name R/W Function ERR_ADR R Retains the address when a PCI bus error occurs. |
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