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UPD703108 Datasheet(PDF) 74 Page - NEC |
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UPD703108 Datasheet(HTML) 74 Page - NEC |
74 / 99 page CHAPTER 5 APPLICATION EXAMPLES Application Note U17121EJ1V1AN 74 ///////////////////////////////////////////////////////////////////////// // Function name: PCI_HBM_Init // // Function: Initializes PCI Host Bridge Macro. // // Argument: None // // Return value: None // // Remark: Base addresses of this initialization sample are as follows.// // - Base address of PCI I/O space: 0C80_0000H // // - Base address of PCI memory space: 0CC0_0000H // // - Base address on PCI bus memory space in which // // main memory (SDRAM) is mapped: 0400_0000H // // - Range of PCI bus memory space in which // // main memory (SDRAM) is mapped: 03FF_FFFFH // // Other settings are required according to system // // requirements and mounting. // ///////////////////////////////////////////////////////////////////////// void PCI_HBM_Init(void) { V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000110; // PCI_CONTROL register // bit 31-24: PCI_PARKCNT = 1 // (Set time for shifting to bus parking to 7) // bit 15-08: PCI_REQ = 1 (Enable I_REQ_B0) // bit 4: PCI_RESET bit = 1 (Release PCI bus reset) V850EME2_REGW(PHBMR_PCI_IO_BASE) = BASE_ADDRESS_PCI_IO; // PCI_IO_BASE register // Set PCI I/O space base address to C800000H. V850EME2_REGW(PHBMR_PCI_MEM_BASE) = BASE_ADDRESS_PCI_MEM; // PCI_MEM_BASE register // Set PCI memory space base address to CC00000H. V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000113; // PCI_CONTROL register // bit 31-24: PCI_PARKCNT = 1 // (Set time for shifting to bus parking to 7) // bit 15-08: PCI_REQ = 1 (Enable I_REQ_B0) // bit 4: PCI_RESET bit = 1 (Release PCI bus reset) // bit 1: PCI_MEM_EN bit = 1 // (Enable access from CPU to PCI memory area) // bit 0: PCI_IO_EN bit = 1 // (Enable access from CPU to PCI I/O area) V850EME2_REGW(PHBMR_SYSTEM_MEM_BASE) = BASE_ADDRESS_SDRAM; // SYSTEM_MEM_BASE register // Set base address on PCI bus memory space in which main // memory (SDRAM) is mapped to 4000000H. |
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