Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
UPD703106A Datasheet(PDF) 59 Page - NEC |
|
UPD703106A Datasheet(HTML) 59 Page - NEC |
59 / 99 page CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION Application Note U17121EJ1V1AN 59 4.4 FPGA Top Pin Functions The pin information when integrating the PCI host bridge macro with an FPGA is shown below. 4.4.1 CPU bus slave interface pins Pin Name I/O Function VBRESETZ Input System reset input CSZ6 Input PCI host bridge chip select input RA0 to RA25 I/O CPU address I/O RD0 to RD31 I/O CPU data I/O BENZ0 to BENZ3 Input CPU data byte enable input WRZ Input CPU data write enable input RDZ Input CPU data read enable input WAITZ Output CPU data wait output INT0 Output PCI host bridge interrupt output 4.4.2 SDRAM bus interface pins Pin Name I/O Function HLDREQZ Output SDRAM bus hold request output HLDACKZ Input SDRAM bus hold acknowledge input SDCLK Input SDRAM clock input SDCKE Output SDRAM clock enable output SDCS Output SDRAM chip select output SDRASZ Output SDRAM row address strobe output SDCASZ Output SDRAM column address strobe output SDWEZ Output SDRAM read/write output DQM0 to DQM3 Output SDRAM output disable output |
Número de pieza similar - UPD703106A |
|
Descripción similar - UPD703106A |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |