VT82C686B
Revision 1.71 June 9, 2000
-33-
Register Overview
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PCI Function 4 Registers - Power Management
Configuration Space Power Management Header
Registers
Offset PCI Configuration Space Header
Default
Acc
1-0
Vendor ID
1106
RO
3-2
Device ID
3057
RO
5-4
Command
0000
RO
7-6
Status
0280
WC
8
Revision ID
nn
RO
9Programming Interface
00
†
RO
A
Sub Class Code
00
†
RO
B
Base Class Code
00
†
RO
C
Cache Line Size
00
RO
D
Latency Timer
00
RO
E
Header Type00
RO
FBIST
00
RO
10-3F -reserved-
00
—
† The default values for these registers may be changed by
writing to offsets 61-63h (see below).
Configuration Space Power Management Registers
Offset Power Management
Default
Acc
40
General Configuration 0
00
RW
41
General Configuration 1
00
RW
42
ACPI Interrupt Select
00
RW
43
Internal Timer Read Test
—
RO
45-44 Primary Interrupt Channel
0000
RW
47-46 Secondary Interrupt Channel
0000
RW
4B-48 Power Mgmt I/O Base (256 Bytes)
0000 0001 RW
4C
Host Bus Power Management Control
00
RW
4D
Throttle / Clock Stop Control
00
RW
4E-4F -reserved-
00
—
53-50 GP Timer Control
0000 0000 RW
54
Power Well Control
00
RW
55
USB Wakeup Control
00
RW
56
-reserved-
00
—
57
Miscellaneous Control
00
RW
58
GP2 / GP3 Timer Control
00
RW
59
GP2 Timer
00
RW
5A
GP3 Timer
00
RW
5B-60 -reserved-
00
—
61
Write value for Offset 9 (Prog Intfc)
00
WO
62
Write value for Offset A (Sub Class)
00
WO
63
Write value for Offset B (Base Class)
00
WO
64-7F -reserved-
00
—
Configuration Space Hardware Monitor Registers
Offset System Management Bus
Default
Acc
71-70 Hardware Mon IO Base (128 Bytes)
0001
RW
72-73 -reserved-
00
—
74
Hardware Monitor Control
00
RW
75-8F -reserved-
00
—
Configuration Space SMBus Registers
Offset System Management Bus
Default
Acc
93-90 SMBus I/O Base (16 Bytes)
0000 0001 RW
94-D1 -reserved-
00
—
D2
SMBus Host Configuration
00
RW
D3
SMBus Host Slave Command
00
RW
D4
SMBus Slave Address Shadow Port 1
00
RW
D5
SMBus Slave Address Shadow Port 2
00
RW
D6
SMBus Revision ID
nn
RO
D7-FF -reserved-
00
—
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