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VT82C686B Datasheet(PDF) 69 Page - List of Unclassifed Manufacturers

No. de pieza VT82C686B
Descripción Electrónicos  PCI Super-I/O Integrated Peripheral Controller
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Fabricante Electrónico  ETC1 [List of Unclassifed Manufacturers]
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VT82C686B Datasheet(HTML) 69 Page - List of Unclassifed Manufacturers

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VT82C686B
Revision 1.71 June 9, 2000
-63-
Function 0 Registers - PCI to ISA Bridge
7HFKQRORJLHV ,QF
'HOLYHULQJ 9DOXH
'HOLYHULQJ 9DOXH
Offset 76 – GPIO Control 3 (00) ......................................RW
7
Over-Current (OC) Input
0
Disable ...................................................default
1
Enable (pins G5 and H3 are USBOC0# and
USBOC1# if bit-6 = 0)
6
OC[3:0] From SD[3:0] By Scan
0
Disable (pins G5 & H3 are USBOC0# and
USBOC1# if bit-7 = 1) ...........................default
1Enable
5
GPO14 / GPO15 Enable (Pins E12 / D12)
0
Pins used for IRTX and IRRX ...............default
1
Pins used for GPO14 and GPO15
4
MCCS# Pin Select
0
MCCS# is on Pin U5 ..............................default
1
MCCS# is on Pin U8
3
MCCS# Function
0
Disable MCCS# function .......................default
1
Enable MCCS# function
(see bit-4 for select of U5 or U8 for MCCS#)
2
CHAS Enable (Pin V14)
0
Pin is defined as GPIOC.........................default
1
Pin is defined as CHAS
1
GPO12 Enable (Pin T5)
0
Pin is defined as XDIR...........................default
1
Pin is defined as GPO12
0
GPOWE# (GPO[23-16]) Enable (Pin T14)
0
Pin is defined as GPIOA ........................default
1
Pin is defined as GPOWE# (Rx74[2] also must
be set to 1)
Offset 77 – GPIO Control 4 Control (10h) ..................... RW
7
DRQ / DACK# Pins are GPI / GPO
0
Disable................................................... default
1Enable
6
Game Port XY Pins are GPI / GPO
0
Disable................................................... default
1Enable
5
Reserved
........................................ always reads 0
4
Internal APIC Enable
0
Disable
1
Enable (U10 = WSC#, V9 = APICD0, T10 =
APICD1)................................................ default
3
IRQ0 Output
0
Disable................................................... default
1
Enable IRQ0 output to GPIOC
2
RTC Rx32 Write Protect
0
Disable................................................... default
1Enable
1
RTC Rx0D Write Protect
0
Disable................................................... default
1Enable
0
GPO13 Enable (Pin U5)
0
Pin defined as SOE# .............................. default
1
Pin defined as GPO13


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