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VT8601 Datasheet(PDF) 49 Page - List of Unclassifed Manufacturers

No. de pieza VT8601
Descripción Electrónicos  Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller
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Fabricante Electrónico  ETC1 [List of Unclassifed Manufacturers]
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VT8601 Datasheet(HTML) 49 Page - List of Unclassifed Manufacturers

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VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-43-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 6C - SDRAM Control .............................RW
7-5
Reserved
........................................ always reads 0
4
CKE Configuration
0
Rx6B[4]=0
RASA = CSA, RASB = CSB,
CKE0=CKE0, CKE1 = CKE1
x
Rx6B[4]=1
RASA = CSA, RASB = Float,
CASB = Float, MAB = Float,
CKE0 = CKE0, CKE1 = CKE0
1
Rx6B[4]=0
RASA = CSA, RASB = CSB,
CKE3-2 = CSA7-6
CKE5-4 = CSB7-6
CKE1 = GCKE (Global CKE)
CKE0 = FENA (FET Enable)
3
Fast AGP TLB lookup
0
Disable ...................................................default
1
Reduce the lookup time from 4T to 2T
2-0
SDRAM Operation Mode Select
000 Normal SDRAM Mode ..........................default
001 NOP Command Enable
010 All-Banks-Precharge Command Enable
(CPU-to-DRAM cycles are converted
to All-Banks-Precharge commands).
011 MSR Enable
CPU-to-DRAM
cycles
are
converted
to
commands and the commands are driven on
MA[13:0]. The BIOS selects an appropriate
host address for each row of memory such that
the
right
commands
are
generated
on
MA[13:0].
100 CBR Cycle Enable (if this code is selected,
CAS-before-RAS refresh is used; if it is not
selected, RAS-Only refresh is used)
101 Reserved
11x Reserved
Rx6B[0] Rx64-66[1-0] Rx68[7-6] Remark
0
00
00
Non-page mode, every access starts
from precharge-active cmd
1
00
00
Only one page active at a time
(recommended setting)
1
01 or 10
00
Only allow sub-bank of a SDRAM
bank active at a time, # of subbank
depends on Rx64-66<1:0>
1
01 or 10
01
Allow mutliple sub-banks across
different SDRAM banks active, but
if EDO is accessed, all SDRAM
pages will be closed
1
01 or 10
11
Allow maximum 8 pages of
SDRAM, EDO opened
Device 0 Offset 6D - DRAM Drive Strength................... RW
7
Reserved
........................................ always reads 0
6-5
Delay DRAM Read Latch
00 Disable................................................... default
01 0.5 ns
10 1.0 ns
11 1.5 ns
4
MD Drive
0
6 mA .................................................... default
18 mA
3
SDRAM Command Drive Strength
(SRAS#, SCAS#, SWE#)
0
16mA .................................................... default
1
24mA
2
MA[2:13] / WE# Drive Strength
0
16mA .................................................... default
1
24mA
1
CAS# Drive Strength
0
8 mA .................................................... default
1
12 mA
0
RAS# Drive Strength
0
16mA .................................................... default
1
24mA


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