VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-46-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 75 - PCI Arbitration 1 ............................RW
7
Arbitration Mechanism
0
PCI has priority ......................................default
1
Fair arbitration between PCI and CPU
6
Arbitration Mode
0
REQ-based (arbitrate at end of REQ#)...default
1
Frame-based (arbitrate at FRAME# assertion)
5-4
Latency Timer ........... read only, reads Rx0D bits 2:1
3-0
PCI Master Bus Time-Out
(force into arbitration after a period of time)
0000 Disable ...................................................default
0001 1x32 PCLKs
0010 2x32 PCLKs
0011 3x32 PCLKs
0100 4x32 PCLKs
...
...
1111 15x32 PCLKs
Device 0 Offset 76 - PCI Arbitration 2............................ RW
7
CPU-to-PCI Post-Write Retry Failed
0
Continue retry attempt ........................... default
1
Go to arbitration
6
CPU Latency Timer Bit-0 ....................................RO
0
CPU has at least 1 PCLK time slot when CPU
has PCI bus ............................................ default
1
CPU has no time slot
5-4
Master Priority Rotation Control
00 Disabled (arbitration per Rx75 bit-7)..... default
01 Grant to CPU after every PCI master grant
10 Grant to CPU after every 2 PCI master grants
11 Grant to CPU after every 3 PCI master grants
With setting 01, the CPU will always be granted
access after the current bus master completes, no
matter how many PCI masters are requesting. With
setting 10, if other PCI masters are requesting during
the current PCI master grant, the highest priority
master will get the bus after the current master
completes, but the CPU will be guaranteed to get the
bus after that master completes. With setting 11, if
other PCI masters are requesting, the highest priority
will get the bus next, then the next highest priority
will get the bus, then the CPU will get the bus. In
other words, with the above settings, even if multiple
PCI masters are continuously requesting the bus, the
CPU is guaranteed to get access after every master
grant (01), after every other master grant (10) or after
every third master grant (11).
3-2
High Priority REQ Select
00 REQ4 .................................................... default
01 REQ0
10 REQ1
11 REQ2
1
CPU-to-PCI QW High DW Read Access to PCI
Slave Allow Backoff
0
Disable................................................... default
1Enable
0
High Priority Request Support
0
Disable................................................... default
1Enable
Device 0 Offset 77 - Chip Test Mode............................... RW
7-6
Reserved (no function) ....................... always reads 0
5-0
Reserved (do not use) ................................. default=0
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