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NM25C04L Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. NM25C04L
Descripción  4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface Synchronous Bus)
Descarga  12 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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NM25C04L Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
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DC and AC Electrical Characteristics 45V s VCC s 55V (unless otherwise specified) (Continued)
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
tHDS
HOLD Setup Time
NM25C04L
200
ns
NM25C04LE
200
ns
tCSN
CS Hold Time
NM25C04L
500
ns
NM25C04LE
500
ns
tDIN
Data Hold Time
100
ns
tHDN
HOLD Hold Time
200
ns
tPD
Output Delay
NM25C04L
CL e 200 pF
500
ns
NM25C04LE
500
ns
tLZ
HOLD to Output Low Z
NM25C04L
500
ns
NM25C04LE
500
ns
tDF
Output Disable Time
NM25C04L
CL e 200 pF
500
ns
NM25C04LE
500
ns
tHZ
HOLD to Output High Z
NM25C04L
500
ns
NM25C04LE
500
ns
tWP
Write Cycle Time
1 – 4 Bytes
10
ms
Capacitance (Note 4)
TA e 25 C f e 1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
3
8
pF
CIN
Input Capacitance
2
6
pF
AC Test Conditions
Output Load
IOL e 10 mA IOH e 10 mA
Input Pulse Levels
03V and 18V
Timing Measurement Reference Level
Input
04V and 16V
Output
08V and 16V
Note 1
Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
The SCK frequency specification specifies a minimum clock period of 1000 ns therefore in an SCK clock cycle tCLH a tCLL must be greater than or equal
to 1000 ns For example if tCLL e 410 ns then the minimum tCLH e 550 ns in order to meet the SCK freqency specification
Note 3
CS must be brought high for a minimum of 500 ns (tCSH) between consecutive instruction cycles
Note 4
This parameter is periodically sampled and not 100% tested
4


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