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NM25C04L Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. NM25C04L
Descripción  4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface Synchronous Bus)
Descarga  12 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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NM25C04L Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Functional Description
MASTER
The device that generates the serial clock is des-
ignated as the master The NM25C04L can never function
as a master
SLAVE
The NM25C04L always operates as a slave as the
serial clock pin is always an input
TRANSMITTERRECEIVER
The NM25C04L has separate
pins for data transmission (SO) and reception (SI)
MSB
The Most Significant Bit is the first bit transmitted and
received
CHIP SELECT
The chip is selected when pin CS is low
When the chip is
not selected data will not be accepted
from pin SI and the output pin SO is in high impedance
SERIAL OP-CODE
The first byte transmitted after the chip
is selected with CS going low contains the op-code that
defines the operation to be performed In the READ and
WRITE instructions the op-code also contains address bit
A8
PROTOCOL
When connected to the SPI port of a 68HC11
microcontroller the NM25C04L accepts only a clock phase
of 1 and a clock polarity of 0 The SPI protocol for this
device defines the bytes transmitted on the SI and SO data
lines for proper chip operation See
Figure 3
TLD11729 – 5
FIGURE 3
Phase 1 CS is held LOW during all serial communications
and is held HIGH only between instructions
Polarity 0 Clock data IN on negative SCK edge and clock
data OUT on positive SCK edge
HOLD
The HOLD pin is used in conjunction with the CS to
select the device Once the device is selected and a serial
sequence is underway HOLD may be forced low to sus-
pend further serial communication with the device without
resetting the serial sequence Note that HOLD must be
brought low while the SCK pin is high The device must
remain selected during this sequence To resume serial
communication HOLD is brought high while the SCK pin is
high Pins SI SCK and SO are at a high impedance state
during HOLD See
Figure 4
TLD11729 – 6
FIGURE 4 HOLD Timing
INVALID OP-CODE
After an invalid code is received no
data is shifted into the NM25C04L and the SO data output
pin remains high impedance until a new CS falling edge re-
initializes the serial communication See
Figure 5
TLD11729 – 7
FIGURE 5
TABLE 1
Instruction
Instruction
Operation
Name
Format
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 A011
Read Data from Memory
Array
WRITE
0000 A010
Write Data to Memory Array
Note
‘‘A’’ represents MSB address bit A8
6


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