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MC100ES6226 Datasheet(PDF) 6 Page - Motorola, Inc

No. de Pieza. MC100ES6226
Descripción  2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider
Descarga  12 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC100ES6226 Datasheet(HTML) 6 Page - Motorola, Inc

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MC100ES6226
MOTOROLA
TIMING SOLUTIONS
6
TABLE 7: AC CHARACTERISTICS (VCC = 3.3V ± 5% and 2.5V ± 5%, TJ = 0°C to +110°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VPP
Differential input voltagec
(peak-to-peak)
0.2
0.3
1.3
V
VCMR
Differential input crosspoint voltaged
1.0
VCC-0.3
V
VX,OUT
Differential output crosspoint voltage
VCC-1.45
VCC-1.1
V
VO(P-P)
Differential output voltage (peak-to-peak)
fO < 300 MHz
fO < 1.5 GHz
fO < 2.7 GHz
0.45
0.3
TBD
0.72
0.55
0.37
0.95
0.95
0.95
V
V
V
fCLK
Input Frequency
0
3000e
MHz
tPD
Propagation Delay CLK to Qx[]
475
500
800
ps
Differential
tsk(O)
Output-to-output skew
(within QA[2:0])
(within QB[2:0])
(within QC[2:0])
(within device)
11
12
4
25
25
20
60
ps
ps
ps
ps
Differential
tsk(PP)
Output-to-output skew
(part-to-part)
325
ps
Differential
tJIT(CC)
Output cycle-to-cycle jitter
single frequency configuration
÷1/÷2 frequency configuration
TBD
TBD
FSEL0 = FSEL1
FSEL0
≠ FSEL1
DCO
Output duty cycle
Qx =
÷1, fO < 300 MHz
Qx =
÷1, fO > 300 MHz
Qx =
÷2, fO < 300 MHz
Qx =
÷2, fO > 300 MHz
48
45
49
47.5
50
50
50
50
52
55
51
52.5
%
%
%
%
DCfref= 50%
tr, tf
Output Rise/Fall Time
0.05
200
ns
20% to 80%
tPDLf
Output disable time
2.5
⋅T + tPD
4.5
⋅T + tPD
ns
T=CLK period
tPLDg
Output enable time
3
⋅T + tPD
5
⋅T + tPD
ns
T=CLK period
a.
AC characterisitics are design targets and pending characterization.
b.
AC characteristics apply for parallel output termination of 50
Ω to VTT.
c.
VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
d.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
e.
The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
f.
Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
g.
Propagation delay OE assertion to output enabled (active).
tPDL (OE to Qx)
Figure 3. MC100ES6226 output disable/enable timing
50%
tPLD (OE to Qx)
Outputs disabled
CLK
CLK
OE
Qx
Qx
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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