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MSM7584D Datasheet(PDF) 16 Page - OKI electronic componets |
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MSM7584D Datasheet(HTML) 16 Page - OKI electronic componets |
16 / 58 page ¡ Semiconductor MSM7584D 16/58 FEDL7584D-02 AFC/RCW AFC operation and clock regeneration range specification signal input. As shown in Figure 5, AFC information is reset when AFC/RCW and RPR go to "1" level. The AFC operation starts after a certain time elapses. The average number of AFC operation times is small when RPR is at "1" level. The average number of AFC operation times is large when RPR is at "0" level. If AFC/RCW is at "0" level, DPLL will not adjust the phase. Figure 5 AFC Control Timing Diagram AFC/RCW AFC information is reset. RPR Averag number of AFC operation times is small. AFC information is maintained. AFC/RCW RPR AFC information is maintained. The clock generation circuit starts with the previous AFC information. "0" (CASE1) (CASE2) Average number of AFC operation times is large. Average number of AFC operation times is large. |
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