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74V1T80STR Datasheet(PDF) 1 Page - STMicroelectronics |
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74V1T80STR Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page  1/9 April 2004 s HIGH SPEED: fMAX = 180MHz (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN), VIL =0.8V (MAX) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =8mA (MIN) at VCC =4.5V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1T80 is an advanced high-speed CMOS SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH INVERTED OUTPUT fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. it is designed to operate from 4.5V to 5.5V, making this device ideal for portable applications. This D-Type flip-flop is controlled by a clock input (CK). On the positive transition of the clock, the Q output will be set to the logic inverted state that was setup at the D input. Following the hold time interval, data at the D input can be changed without affecting the level at the output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V. It’s available in the commercial temperature range. All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. 74V1T80 SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74V1T80STR SOT323-5L 74V1T80CTR SOT323-5L SOT23-5L |
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