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MC908QY1A Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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MC908QY1A Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 200 page  Low-Power Modes MC68HC908QYA/QTA Family Data Sheet, Rev. 0 Freescale Semiconductor 53 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. The AWU counters start from 0 each time wait mode is entered. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start from 0 each time stop mode is entered. 4.6 Registers The AWU shares registers with the keyboard interrupt (KBI) module, the port A I/O module and configuration register 2. The following I/O registers control and monitor operation of the AWU: • Port A data register (PTA) • Keyboard interrupt status and control register (KBSCR) • Keyboard interrupt enable register (KBIER) • Configuration register 1 (CONFIG1) • Configuration register 2 (CONFIG2) 4.6.1 Port A I/O Register The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition to the data latches for port A. AWUL — Auto Wakeup Latch This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally. There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits. 1 = Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending NOTE PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 12.2.1 Port A Data Register. Bit 7 654321 Bit 0 Read: 0 AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: 0 0 Unaffected by reset = Unimplemented Figure 4-2. Port A Data Register (PTA) |
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