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STK16C68-W25I Datasheet(Hoja de datos) 7 Page - List of Unclassifed Manufacturers

No. de Pieza. STK16C68-W25I
Descripción  8K x 8 AutoStorePlus™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM
Descarga  9 Pages
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Fabricante  ETC1 [List of Unclassifed Manufacturers]
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July 1999
The AutoStorePlus™ STK16C68 is a fast 8K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
while power is unavailable. The nonvolatil-
ity of the STK16C68 does not require any system
intervention or support: AutoStorePlus™ on power-
down and automatic RECALL on power-up guaran-
tee data integrity without the use of batteries.
Note that the STK16C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1
µF connected between V
and V
SS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
The STK16C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of t
AVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at t
at t
GLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the t
AVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high or W is brought low.
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7 will be writ-
ten into the memory if it is valid t
DVWH before the end
of a W controlled WRITE or t
DVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
AutoStorePlus™ OPERATION
The STK16C68’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
CC < VSWITCH) at which point the part
depends only on its internal capacitor for STORE
completion. This safe transfer of data from SRAM to
takes place regardless of power supply
slew rate.
In order to prevent unneeded STORE operations, the
automatic STORE will be ignored unless at least one
operation has taken place since the most
recent STORE or RECALL cycle. Software-initiated
cycles are performed regardless of whether
or not a WRITE operation has taken place.
During power up, or after any low-power condition
CC < VRESET), an internal RECALL request will be
latched. When V
CC once again exceeds the sense
voltage of V
SWITCH, a RECALL cycle will automatically
be initiated and will take t
RESTORE to complete.
If the STK16C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10k
Ω resistor should
be connected either between W and system V
CC or
between E and system V
The STK16C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
sequence must be performed:

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