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AK6516C Datasheet(PDF) 8 Page - Asahi Kasei Microsystems

No. de Pieza. AK6516C
Descripción  SPI bus 256Kbit Serial CMOS EEPROM
Descarga  17 Pages
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Fabricante  AKM [Asahi Kasei Microsystems]
Página de inicio  http://www.akm.com
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AK6516C Datasheet(HTML) 8 Page - Asahi Kasei Microsystems

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ASAHI KASEI
[AK6516C]
DAP05E-00
2005/03
- 8 -
WRITE (WRITE SEQUENCE)
WRITE instruction can start the WRITE function to the memory cell array.
After CS pin changes high to low, op-code, address and data are input from SI pin.
After the
instruction input, the internal programming cycle starts when CS pin changes low to high.
After the
instructions are inputted, CS pin should change low to high after the last data bit (D0) inputs and
before next SCK clock rises.
Write function can start only at this timing.
AK6516C can indicate the BUSY status by using RDSR instruction and READ the RDY bit (Bit0) in
the status register.
RDY is "1" indicates AK6516C is in the programming cycle, and RDY is "0"
indicates AK6516C is in the READY status.
AK6516C outputs the "FF" when RDSR instruction
executes during the programming cycle.
Only RDSR instruction can be accepted during
programming cycle.
AK6516C has Page Write mode, which can write the data within 64 bytes with one programming
cycle.
The input data sent to the shift register within 64 bytes.
If the number of bytes exceeded
64, the address counter rolls over to the first address of the page.
Internal programming cycle starts after CS pin changes low to high.
After WRITE instruction, AK6516C changes to Write Disable status automatically.
AK6516C needs
WREN instruction before every WRITE instruction.
When WRITE instruction is done while
AK6516C is in Write Disable status, WRITE instructions are ignored and AK6516C becomes
standby status after CS changes to high.
AK6516C can accept the next instruction after CS
becomes low.
WRITE instruction cannot write the data into the address of the protected block.
WRITE
Hi-Z
32
33
34
35
36
37
38
39
40
0
1
2
3
4
5
6
7
8
9
10
11
12
13
23
22
0
0
0
0
0
1
0
A0
A1
A10
Hi-Z
CS
SCK
SI
SO
A11
24
25
30
31
D0
D1
D6
D7
Data(n)
CS
SCK
SI
SO
X = don’t care
Data(n+1)
D0
D1
D6
D7
D4
D5
D3
D2
D7
Data(n+63)
D0
D0
D1
D6
D7
D4
D5
D3
D2
A12
X
X A14 A13


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