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SMS48GCR00 Datasheet(PDF) 11 Page - Summit Microelectronics, Inc.

No. de pieza SMS48GCR00
Descripción Electrónicos  Quad Programmable Precision Supervisory Controller With Independent Resets
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Fabricante Electrónico  SUMMIT [Summit Microelectronics, Inc.]
Página de inicio  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMS48GCR00 Datasheet(HTML) 11 Page - Summit Microelectronics, Inc.

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11
2088 1.1 04/11/05
SMS48
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 8. I2C Operating Characteristics
Figure 7 - I2C Operating Characteristics
I2C INTERFACE
Note (1): These values are guaranteed by design.
CONFIGURATION REGISTER OPERATION
Data for the configuration registers are read and written via
an industry standard two-wire interface. The bus was
designed for two-way, two-line serial communication be-
tween different integrated circuits. The two lines are a
serial data line (SDA) and a serial clock line (SCL). The
SDA line must be connected to a positive supply by a pull-
up resistor, located somewhere on the bus. See Operating
Characteristics: Table 8 and Figure 7.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS48 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
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