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SMS46GCR03 Datasheet(PDF) 11 Page - Summit Microelectronics, Inc. |
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SMS46GCR03 Datasheet(HTML) 11 Page - Summit Microelectronics, Inc. |
11 / 17 page 11 2083 1.1 06/04/04 SMS46 SUMMIT MICROELECTRONICS, Inc. Preliminary Information Table 8. Memory Operating Characteristics 2047 Table10 4.0 Figure 7 - Memory Operating Characteristics I2C INTERFACE Note (1): These values are guaranteed by design. MEMORY OPERATION Data for the configuration registers and the memory array are read and written via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated cir- cuits. The two lines are a serial data line (SDA) and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located some- where on the bus. See Memory Operating Characteris- tics: Table 8 and Figure 7. Input Data Protocol The protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. In all cases the SMS46 will be a Slave device, since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time because changes on the data line while SCL is high will be interpreted as start or stop condition. tF tR tLOW tHIGH tHD:STA tSU:STA tBUF tDH tHD:DAT tSU:DAT tSU:STO SCL SDA In SDA Out tAA 2047 Fig09 l o b m y Sr e t e m a r a Ps n o i t i d n o CN I MP Y TX A Ms t i n U f L C S y c n e u q e r f k c o l c L C S 00 0 1z H k t W O L d o i r e p w o l k c o l C 7 . 4s µ t H G I H d o i r e p h g i h k c o l C 0 . 4s µ t F U B ) 1 ( e m i t e e r f s u Bn o i s s i m s n a r t w e n e r o f e B7 . 4s µ t A T S : U S e m i t p u t e s n o i t i d n o c t r a t S 7 . 4s µ t A T S : D H e m i t d l o h n o i t i d n o c t r a t S 0 . 4s µ t O T S : U S e m i t p u t e s n o i t i d n o c p o t S 7 . 4s µ t A A t u p t u o d il a v o t e g d e k c o l C) n e l c y c ( A D S d il a v o t w o l L C S2 . 05 . 3s µ t H D e m i t d l o h t u O a t a De g n a h c A D S o t ) 1 + n e l c y c ( w o l L C S2 . 0s µ t R ) 1 ( e m i t e s i r A D S d n a L C S 0 0 0 1s n t F ) 1 ( e m i t ll a f A D S d n a L C S 0 0 3s n t T A D : U S e m i t p u t e s n I a t a D 0 5 2s n t T A D : D H e m i t d l o h n I a t a D 0s n I TA D S d n a L C S r e t li f e s i o Nn o i s s e r p p u s e s i o N0 0 1s n t R W e m i t e l c y c e t i r W 5s m |
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