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SMM766FCR7 Datasheet(PDF) 11 Page - Summit Microelectronics, Inc.

No. de pieza SMM766FCR7
Descripción Electrónicos  Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link?
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Fabricante Electrónico  SUMMIT [Summit Microelectronics, Inc.]
Página de inicio  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMM766FCR7 Datasheet(HTML) 11 Page - Summit Microelectronics, Inc.

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SMM766
Preliminary Information
Summit Microelectronics, Inc
2086 2.1 12/13/2005
11
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 5
and 6 Timing diagrams.
Symbol
Description
Conditions
Min
Typ
Max
Unit
TDPON = 0.64MS
TDPON = 12.5MS
TDPOFF = 25MS
tDPON
Programmable power-on delay
from restart timer expiration to
PUPY active
TDPOFF = 50MS
-25
tDPON
+25
%
TDPOFF = 0.64MS
tDPOFF
Programmable power-off delay
from VMX off to PUPY inactive
TDPOFF = 12.5MS
-25
tDPOFF
+25
%
TPRTO = 0.64MS
TPRTO = 25MS
TPRTO = 100MS
tPRTO
Programmable reset time-out delay
TPRTO = 200MS
-25
tPRTO
+25
%
TSTT = OFF
TSTT = 100MS
TSTT = 200MS
tSTT
Programmable sequence
termination timer
TSTT = 400MS
-25
tSTT
+25
%
tFTRD
Fault-triggered restart delay
Time from restart timer
expiration to PUPY active
after a fault-triggered power-
off or force-shutdown.
2.4
s
tFTRDACC
Fault-triggered restart delay
accuracy
-25
tFTRD
+25
%
tCTRD
Command-triggered restart delay
Time from restart timer
expiration to PUPY active
after command-triggered
power-off or force-shutdown.
12.5
ms
tCTRDACC
Command-triggered restart delay
accuracy
-25
tCTRD
+25
%
TADC
10-bit ADC sampling period
Time for ADC conversion of
all 11 channels
2.0
ms
TDC_CONTROL
ADOC sampling period
Update period for ADOC of
channels
A – F
1.7
ms
Slow Margin, + 10% change
in voltage with 0.1% ripple
TRIM_CAP=1
µF
850
ms
tMARGIN
Margin Time from Nominal
Fast Margin, + 10% change
in voltage with 0.1% ripple
TRIM_CAP=1
µF
85
ms
AC OPERATING CHARICTERISTICS


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