SMS48GR05 datasheet(8/16 Pages) SUMMIT

No. de pieza	SMS48GR05

Descripción Electrónicos	Quad Programmable Precision Supervisory Controller With Independent Resets

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Fabricante Electrónico	SUMMIT [Summit Microelectronics, Inc.]

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8 / 16 page

8

SMS48

2088 1.1 04/10/05

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

Table 2. Configuration Register 4

DEVICE OPERATION AND CONFIGURATION REGISTERS

SUPPLY AND MONITOR FUNCTIONS

The V0, V1, V2, and V3 inputs are internally ORed so that

any one of the four can act as the device supply. The

RESET# outputs will be guaranteed true so long as one of

the four pins is at or above 1V.

Note: for performing a Read or Write operation and

to have the ability to change configuration register

contents at least one supply input must be above

2.7V.

Read/Write operations require a 0.1µF capacitor from the

VDD_CAP node to GND. For optimum performance

connect capacitors from each of the Vx inputs to GND.

Locate the capacitors as physically close to the SMS48 as

possible.

Associated with each input is a comparator with a program-

mable threshold for detection of under-voltage or over-

voltage conditions on any of the four supply inputs. The

threshold can be programmed in 5mV increments any-

where within the range of 0.6V to 1.875V or 15mV incre-

ments within the range of 1.8V to 5.625V. Configuration

registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2,

and V3 respectively.

If the value contained in any register is all zeroes, the

corresponding threshold will be 0.6V. If the contents were

low range 05HEX the threshold would then be 0.625V [0.6V

+ (5

× 0.005V)]. All four registers are configured as 8-Bit

registers.

Table 1. Configuration Registers 0, 1, 2, and 3

RESET# FUNCTION

Each RESET# output has a programmable source for

activation. Configuration register 4 is used for enabling the

activation source. A monitor input can be programmed to

activate on either an under-voltage or over-voltage condi-

tion, but not both conditions. When this condition ceases,

each individual RESET# output will remain active for tPRTO

(programmable reset time-out). The reset threshold voltage

range for V0 to V3 can be set for 5mV increments below

1.875V (low Range = "0") or for 15mV increments above

1.8V (high range = "1") using Bits D3:0.

The RESET#0-3 outputs have two hardwired sources for

activation: the MR# input and Watchdog timer. All

RESET# outputs will remain active so long as MR# is low,

and will continue driving the RESET# outputs for tPRTO

(programmable reset time out) after MR# returns high. The

MR# input cannot be bypassed or disabled.

Refer to Figures 1, 2 and 3 for a detailed illustration of the

relationships among the affected signals.

The SMS48 provides the option of the monitors triggering

on either an under-voltage or over-voltage condition. The

low-order four bits of configuration register 5 program these

options.

WATCHDOG TIMER

The SMS48 contains an independent timer that can be

programmed. The Watchdog generates all RESET#s if it

times out. The timer is cleared by a low to high transition

on WLDI and will reset all four RESET#.

If the watchdog should time-out the device status can be

monitored in the status register (Table 4). Refer to Figure

3 which illustrates the action of RESET#0-3 with respect to

the Watchdog timer and the WLDI input.

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