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TPS65161 Datasheet(PDF) 6 Page - Texas Instruments

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No. de pieza TPS65161
Descripción Electrónicos  BIAS POWER SUPPLY FOR TV AND MONITOR TFT LCD PANELS
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TPS65161
SLVS617 – APRIL 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
This is the supply pin of the positive charge pump driver and can be connected to the input supply Vin or the
SUP
8
I
output of the main boost converter Vs. This depends mainly on the desired output voltage VGH and numbers of
charge pump stages.
Frequency adjust pin. This pin allows setting the switching frequency with a logic level to 500 kHz = low and
FREQ
12
I
750 kHz = high.
Analog input voltage of the device. This is the input for the analog circuits of the device and should be bypassed
AVIN
22
I
with a 1-
µF ceramic capacitor for good filtering.
VINB
20, 21
I
Power input voltage pin for the buck converter.
This is the enable pin of the buck converter and negative charge pump. When this pin is pulled high, the buck
EN1
16
I
converter starts up, and after a delay time set by DLY1, the negative charge pump comes up. This pin must be
terminated and not be left floating. A logic high enables the device and a logic low shuts down the device.
The boost converter starts only with EN1 = high, after the step-down converter is enabled. EN2 is the enable pin
of the boost converter and positive charge pump. When this pin is pulled high, the boost converter and positive
EN2
9
I
charge pump starts up after the buck converter is within regulation and a delay time set by DLY2 has passed by.
This pin must be terminated and not be left floating. A logic high enables the device and a logic low shuts down
the device.
DRN
11
O
Drive pin of the negative charge pump.
FBN
13
I
Feedback pin of negative charge pump.
REF
24
O
Internal reference output typically 1.213 V
PGND
6, 7
Power ground
This pin allows setting the soft-start time for the main boost converter VS. Typically a 22-nF capacitor needs to be
SS
28
O
connected to this pin to set the soft-start time.
Connecting a capacitor from this pin to GND allows the setting of the delay time between VLOGIC (step-down
DLY1
25
O
converter output high) to VGL during start-up.
Connecting a capacitor from this pin to GND allows the setting of the delay time between VLOGIC (step-down
DLY2
26
O
converter output high) to VS Boost converter and positive charge-pump VGH during start-up.
This is the compensation pin for the main boost converter. A small capacitor and, if required, a resistor is
COMP
2
connected to this pin.
FBB
15
I
Feedback pin of the buck converter
SWB
18
O
Switch pin of the buck converter
NC
19
Not connected
N-channel MOSFET gate drive voltage for the buck converter. Connect a capacitor from the switch node SWB to
BOOT
17
I
this pin.
FBP
14
I
Feedback pin of positive charge pump.
DRP
10
O
Drive pin of the positive charge pump.
This is the gate drive pin which can be used to control an external MOSFET switch to provide input to output
isolation of VS or VGH. See the circuit diagrams at the end of this data sheet. GD is an open-drain output and is
GD
27
latched low as soon as the boost converter is within 8% of its nominal regulated output voltage. GD goes high
impedance when the EN2 input voltage is cycled low.
GND
23
Analog ground
Output sense pin. The OS pin is connected to the internal rectifier switch and overvoltage protection comparator.
This pin needs to be connected to the output of the boost converter and cannot be connected to any other voltage
OS
3
I
rail. Connect a 470-nF capacitor from OS pin to GND to avoid noise coupling into this pin. The PCB trace of the
OS pin needs to be wide because it conducts high current.
FB
1
I
Feedback of the main boost converter generating Vsource (VS).
SW
4, 5
I
Switch pin of the boost converter generating Vsource (VS).
PowerPAD
The PowerPAD needs to be connected and soldered to power ground (PGND).
6
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