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TSI-2 Datasheet(PDF) 27 Page - Agere Systems |
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TSI-2 Datasheet(HTML) 27 Page - Agere Systems |
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27 / 61 page  Data Sheet, Revision 3 TSI-2 September 21, 2005 2k x 2k Time-Slot Interchanger Agere Systems Inc. 27 Figure 5-15. CHI 3-State Output Control Table 5-5. CHI 3-State Output Control Control in the table below refers to bits [6:4] in Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page 52. This only applies if bits 13 and 12 of the corresponding register in Table 6-48 Transmit_CHI_Configuration (Read/Write) on page 50 are set to 11. Parameter Control Reference Point* * Like edge is the reference edge (rising or falling) as defined by bit 0 in Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page 52. Min Max* Unit t20 000 After Previous Like Edge in 16 MHz 50 59 ns 001 After Previous Like Edge in 16 MHz 44 53 ns 010 After Previous Like Edge in 16 MHz 38 47 ns 011 After Previous Like Edge in 16 MHz 32 41 ns t21 000 After Previous Opposite Edge in 8 MHz 50 59 ns 001 After Previous Opposite Edge in 8 MHz 44 53 ns 010 After Previous Opposite Edge in 8 MHz 38 47 ns 011 After Previous Opposite Edge in 8 MHz 32 41 ns t22 100 After Previous Like Edge (8 MHz mode only) 111 120 ns 101 After Previous Like Edge (8 MHz mode only) 105 114 ns 110 After Previous Like Edge (8 MHz mode only) 99 108 ns 111 After Previous Like Edge (8 MHz mode only) 93 102 ns CHICLK 16.384 MHz t20 TXD 16.384 Mbits/s CHICLK 8.192 MHz TXD 8.192 Mbits/s CHICLK 8.192 MHz TXD 8.192 Mbits/s t21 t22 |
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