 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TSI-2 Datasheet(PDF) 41 Page - Agere Systems |
|
||||||||||||||||||||||||||||||
TSI-2 Datasheet(HTML) 41 Page - Agere Systems |
|
|
41 / 61 page  Data Sheet, Revision 3 TSI-2 September 21, 2005 2k x 2k Time-Slot Interchanger Agere Systems Inc. 41 Table 6-27. CSG_Seed_Low (Read/Write) Seed value for the pseudorandom pattern generator for the low word of the connection store RAM. Table 6-28. CSG_Seed_High (Read/Write) Seed value for the pseudorandom pattern generator for the high word of the connection store RAM. Table 6-29. CSG_OR_Mask_Low (Read/Write) This register allows bits in the connection store to be forced to 1. CS[15:0] = (pseudorandom data [15:0] OR CSG_OR_Mask_Low) AND CSG_AND_Mask_Low, bit enabled by CSG_Write_Enable_Low. Table 6-30. CSG_OR_Mask_High (Read/Write) This register allows bits in the connection store to be forced to 1. CS[31:16] = (pseudorandom data [31:16] OR CSG_OR_Mask_High) AND CSG_AND_Mask_High, bit enabled by CSG_Write_Enable_High. Note: CS[22:18] are always 0. Address Bit Name/Description Default 0x00410 15:0 CSG_Seed_Low. If the LFSR_Seed_Control bit (see Table 6-21 on page 39) is asserted, at the beginning of a CSG operation, bits [15:0] of the LFSR supplying the connection store RAM with data are loaded with this programmable seed. 0xFFFF Address Bit Name/Description Default 0x00412 15 Unused. — 14:0 CSG_Seed_High. If the LFSR_Seed_Control bit (see Table 6-21) is asserted, at the begin- ning of a CSG operation, bits [30:16] of the LFSR supplying the connection store RAM with data are loaded with this programmable seed. 0x7FFF Address Bit Name/Description Default 0x00418 15:0 CSG_OR_Mask_Low. This register allows bit fields in the connection store to be forced to a one during a CSG fill operation. A bit-wise OR of this register and bits [15:0] of the pseudo- random generated data are performed to obtain the data for connection store. The resultant is then ANDed with CSG_AND_Mask_Low. 0x0000 Address Bit Name/Description Default 0x0041A 15:7 CSG_OR_Mask_High_B. This register allows bit fields in the connection store to be forced to a 1 during a CSG fill operation. A bit-wise OR of this register and bits [31:23] of the pseu- dorandom generated data are performed to obtain the data for connection store. The result- ant is then ANDed with CSG_AND_Mask_High. 0x000 6:2 Unused. — 1:0 CSG_OR_Mask_High_A. This register allows bit fields in the connection store to be forced to a 1 during a CSG fill operation. A bit-wise OR of this register and bits [17:16] of the pseu- dorandom generated data are performed to obtain the data for connection store. The result- ant is then ANDed with CSG_AND_Mask_High. 00 |
Número de pieza similar - TSI-2 |
|
Descripción similar - TSI-2 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
