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TAA2008 Datasheet(PDF) 4 Page - Tripath Technology Inc. |
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TAA2008 Datasheet(HTML) 4 Page - Tripath Technology Inc. |
4 / 18 page Tri p ath Techn o l o g y, I n c. - T echn i cal I n fo rmation 4 TAA2008 –KLi/1.0/05.06 P I N DE SCRI PTI ON T AA2 00 8 PI N O U T Pin Function Description 1, 29 OAOUT2, OAOUT1 Input stage output pins. 2, 30 INV2, INV1 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with approximately 2.4VDC bias. 3 BIASCAP Input stage bias voltage (approximately 2.4VDC). 4, 24, 27 AGND3, AGND1, AGND2 Analog Ground 5 SLEEP When set to logic high, device goes into low power mode. If not used, this pin should be grounded 6 FAULT A logic high output indicates thermal overload, or an output is shorted to ground, or another output. 7, 18 PGND2, PGND1 Power Grounds (high current) 8 DGND Digital Ground. Connect to AGND locally (near the TAA2008). 10, 12; 15, 13 OUTP2 & OUTM2; OUTP1 & OUTM1 Bridged output pairs 11, 14 VDD2, VDD1 Supply pins for high current H-bridges, nominally 12VDC. 17 VDDA Analog 12VDC. Connect to same supply as VDD1 and VDD2. 19 CPUMP Charge pump output (nominally 10V above VDDA) 20 5VGEN Regulated 5VDC source used to supply power to the input section (pins 23 and 28). 21,22 DCAP2, DCAP1 Charge pump switching pins. DCAP1 (pin 22) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 21) is level shifted 10 volts above DCAP1 (pin 22) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. 23, 28 V5D, V5A Digital 5VDC, Analog 5VDC 25 REF Internal reference voltage; approximately 1.0 VDC. 26 OVERLOADB A logic low output indicates the input signal has overloaded the amplifier. 31 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. 9, 16, 32 NC Not connected. Not bonded internally. PGND1 5VGEN DCAP2 DCAP1 V5D AGND1 INV2 DGND PGND2 FAULT SLEEP AGND3 BIASCAP 18 17 1 8 7 6 5 4 3 2 32-pin QFN (Top View) OAOUT2 24 19 20 21 22 23 CPUMP VDDA |
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