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MX29LV64XMH Datasheet(PDF) 2 Page - Macronix International

No. de Pieza. MX29LV64XMH
Descripción  64M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY
Descarga  70 Pages
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Fabricante  MCNIX [Macronix International]
Página de inicio  http://www.macronix.com
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MX29LV64XMH Datasheet(HTML) 2 Page - Macronix International

 
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P/N:PM1093
REV. 1.1, AUG. 11, 2005
MX29LV64xM H/L
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV64xM H/L uses a command register to manage
this functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV64xM H/L uses a 2.7V to 3.6V
VCC supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC PROGRAMMING
The MX29LV64xM H/L is byte/word/page programmable
using the Automatic Programming algorithm. The Auto-
matic Programming algorithm makes the external sys-
tem do not need to have time out sequence nor to verify
the data programmed.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA# polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prior to electrical erase. The timing and veri-
fication of electrical erase are controlled internally within
the device.
AUTOMATIC SECTOR ERASE
The MX29LV64xM H/L is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically programs
the specified sector(s) prior to electrical erase. The tim-
ing and verification of electrical erase are controlled inter-
nally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV64xM H/L
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.


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