Philips Semiconductors

Product specification

74ABT16240A

74ABTH16240A

16-bit inverting buffer/driver (3-State)

1998 Feb 25

5

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

to +85

°C

UNIT

Min

Typ

Max

Min

Max

Input clamp voltage

–0.9

–1.2

–1.2

V

2.5

2.9

2.5

V

High-level output voltage

3.0

3.4

3.0

V

2.0

2.4

2.0

V

Low-level output voltage

0.42

0.55

0.55

V

Input leakage current

±0.01

±1.0

±1.0

µA

I

Input leakage current

Control

pins

±0.01

±1

±1

µA

In ut leakage current

74ABTH16240A

Data pins

0.01

1

1

µA

Data ins

–2

–3

–5

µA

Bus Hold current A inputs

50

50

Bus Hold current A inputs

–75

–75

µA

74ABTH16240A

±500

Power-off leakage current

±5.0

±100

±100

µA

Power-up/down 3-State

output current

±5.0

±50

±50

µA

3-State output High current

1.0

10

10

µA

3-State output Low current

–1.0

–10

–10

µA

Output high leakage current

1.0

50

50

µA

–50

–70

–180

–50

–180

mA

0.5

1.0

1.0

mA

Quiescent supply current

8

19

19

mA

Quiescent su

ly current

0.5

1.0

1.0

mA

Additional supply current per

Outputs enabled, one input at 3.4V, other

10

200

200

µA

Additional supply current per

Outputs enabled, one input at 3.4V, other

0.2

1.0

1.0

mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. This is the bus hold overdrive current required to force the input to the opposite logic state.

AC CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

WAVEFORM

UNIT

Min

Typ

Max

Min

Max

Propagation delay

nAx to nYx

1

1.0

1.0

2.0

1.5

3.0

3.0

1.0

1.0

3.7

3.5

ns

Output enable time

to High and Low level

2

1.2

1.2

2.4

2.3

3.3

3.2

1.2

1.0

4.2

4.2

ns

Output disable time

from High and Low level

2

1.3

1.3

2.7

2.5

4.1

3.6

1.6

1.4

4.7

4.1

ns