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74ABT16500CDL Datasheet(PDF) 2 Page - NXP Semiconductors

No. de pieza 74ABT16500CDL
Descripción Electrónicos  18-bit universal bus transceiver 3-State
Download  12 Pages
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Fabricante Electrónico  PHILIPS [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ABT16500CDL Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
2
1998 Feb 27
853-1800 19027
FEATURES
18-bit bidirectional bus interface
3-State buffers
74ABTH16500C incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Output capability: +64mA/-32mA
TTL input and output switching levels
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
Negative edge-triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, or latched modes.
DESCRIPTION
The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Two options are available, 74ABT16500C which does not have the
bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF;
VCC = 5V
2.1
1.7
ns
CIN
Input capacitance (Control pins)
VI = 0V or VCC
3
pF
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0V or VCC
7
pF
ICCZ
Quiescent supply current
Outputs disabled; VCC = 5.5V
500
µA
ICCL
Quiescent su
ly current
Outputs low; VCC = 5.5V
8
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ABT16500C DL
BT16500C DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ABT16500C DGG
BT16500C DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ABTH16500C DL
BH16500C DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ABTH16500C DGG
BH16500C DGG
SOT364-1


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