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GS820V32T Datasheet(PDF) 3 Page - GSI Technology |
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GS820V32T Datasheet(HTML) 3 Page - GSI Technology |
3 / 15 page Rev. 9/09/97 3/15 64K x 32 Burst GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA 80-133MHz (P/L) 66MHz Flow-Thru G S I T E C H N O L O G Y GS820V32Q/T Mode pin function LBO Function L Linear Burst H or NC Interleaved Burst FT Function L Flow-Thru H or NC Pipeline Power down control Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. ZZ Function L or NC Active H Standby IDD=ISB Linear Burst sequence The burst wrap around to initial state upon completion A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst sequence The burst wrap around to initial state upon completion A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Byte Write Function Note: H=logic high, L=logic low, NC= no connect Function SGW BWE BW1 BW2 BW3 BW4 Read H H X X X X Read H L H H H H Write all bytes L X X X X X Write all bytes H L L L L L Write byte 1 H L L H H H Write byte 2 H L H L H H Write byte 3 H L H H L H Write byte 4 H L H H H L |
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