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AD5243BRM50 Datasheet(PDF) 5 Page - Analog Devices

No. de pieza AD5243BRM50
Descripción Electrónicos  Dual 256-Position I2C Compatible Digital Potentiometer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD5243BRM50 Datasheet(HTML) 5 Page - Analog Devices

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AD5243/AD5248
Rev. 0 | Page 5 of 20
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = 5V ± 10%, or 3V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS10 (Specifications Apply to All Parts)
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time between STOP and START
t1
1.3
µs
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock pulse is
generated.
0.6
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Setup Time for Repeated START Condition
t5
0.6
µs
tHD;DAT Data Hold Time11
t6
0.9
µs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for STOP Condition
t10
0.6
µs
See notes at end of section.
NOTES
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 5 V.
10See timing diagrams for locations of measured values.
11The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.


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