TLK3104SA

QUAD 3.125 Gbps SERIAL TRANSCEIVER

SCAS651B-– AUGUST 2000 – REVISED SEPTEMBER 2001

4

POST OFFICE BOX 655303

system block diagram (continued)

Figure 3 shows an example system block diagram for TLK3104SA used to provide the system backplane

interconnect.

MAC/

Packet

Processor

XGMII

XAUI

4

TLK3104SA

TX+

TX–

RX+

RX–

TDA..D(0:9)

TCA..D

RCA..D

4

4

4

RDA..D(0:9)

Framer/

PCS

PHY/

Optics

Switch Fabric

XGMII

XAUI

4

TLK3104SA

TX+

TX–

RX+

RX–

TDA..D(0:9)

TCA..D

RCA..D

4

4

4

RDA..D(0:9)

System

Backplane

Line Card

Figure 3. System Block Diagram (Backplane Interconnect Implementation)

The TLK3104SA supports the IEEE802.3 defined management data input/output (MDIO) Interface to allow

ease in configuration and status monitoring of the link. It does not currently support the proposed changes to

the management interface in the IEEE P802.3ae D2.0 Clause 45.

The TLK3104SA supports the IEEE 1149.1 defined JTAG test port for ease in board manufacturing test. It also

supports a comprehensive series of built-in tests for self-test purposes including internal serial loopback and

PRBS generation and verification.

The TLK3104SA operates with a single 2.5-V supply and dissipates less than 3.0 watts. The device is packaged

in a 19x19 mm, 289-pin plastic ball grid array (PBGA) package and is characterized for operation from 0

°C to

70

°C.