Philips Semiconductors

Preliminary specification

74ALVCH16952

16-bit registered transceiver (3-State)

2

1998 Sep 01

FEATURES

minimum noise and ground bounce

DESCRIPTION

The 74ALVCH16952 consists of two sections, each containing a

dual octal non-inverting registered transceiver. Two 8-bit back to

back registers store data flowing in both directions between two

bi-directional busses. Data applied to the inputs is entered and

present at the 3-State output buffers, but is only accessible when the

outputs is the same as for B inputs to A outputs.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

CPnn, to An, Bn

V

25V C

30pF

3.2

ns

Maximum clock frequency

350

MHz

Input capacitance

3.0

pF

Power dissipation capacitance per buffer

30

pF

NOTES:

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

56-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVCH16952 DGG

ACH16952 DGG

SOT364-1

FUNCTION TABLE for register An or Bn

INPUTS

INTERNAL

OPERATING

An or Bn

Q

MODE

X

X

H

NC

Hold data

L

°

L

L

Load data

H

°

L

H

Load data

H = HIGH voltage level

L = LOW voltage level

↑ = LOW-to-HIGH transition

FUNCTION TABLE for output enable

INPUTS

INTERNAL

An or Bn

OPERATING

Q

OUTPUTS

MODE

H

X

Z

Disable outputs

L

L

L

Enable outputs

L

H

H

Enable outputs

NC = no change

X = don’t care

Z = high impedance OFF-state