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74ALVT16601DL Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ALVT16601DL Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 14 page Philips Semiconductors Product specification 74ALVT16601 2.5V/3.3V 18-bit universal bus transceiver (3-State) 2 1998 Feb 13 853-1885 18958 FEATURES • 18-bit bidirectional bus interface • 5V I/O Compatible • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Positive edge triggered clock inputs • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ALVT16601 is a high-performance BiCMOS product designed for VCC operation at 2.5V and 3.3V with I/O compatibility up to 5V. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYPICAL UNIT SYMBOL PARAMETER Tamb = 25°C 2.5V 3.3V UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF 1.9 2.5 1.5 1.9 ns CIN Input capacitance (Control pins) VI = 0V or VCC 4 4 pF CI/O I/O pin capacitance Outputs disabled; VI/O = 0V or VCC 8 8 pF ICCZ Total supply current Outputs disabled 40 60 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVT16601 DL AV16601 DL SOT371-1 56-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVT16601 DGG AV16601 DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 27 OEAB/OEBA A-to-B/ B-to-A Output enable input (active Low) 29, 56 CEBA/CEAB B-to-A/A-to-B clock enable 2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input 55,30 CPAB/CPBA A-to-B/B-to-A Clock input (active rising edge) 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 A0-A17 Data inputs/outputs (A side) 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 B0-B17 Data inputs/outputs (B side) 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage |
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