Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADP3192 Datasheet(PDF) 10 Page - Analog Devices |
|
ADP3192 Datasheet(HTML) 10 Page - Analog Devices |
10 / 32 page ADP3192 Rev. 0 | Page 10 of 32 THEORY OF OPERATION The ADP3192 combines a multimode, fixed frequency, PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11-compatible and 7-bit VRD/VRM 10×-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3192 ensures a stable, high performance topology for the following: • Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and output decoupling • Minimizing thermal switching losses by using lower frequency operation • Tight load line regulation and accuracy • High current output due to 4-phase operation • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance START-UP SEQUENCE The ADP3192 follows the VR11 start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first five clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2), and the output comes up to the boot voltage of 1.1 V. The boot hold time is determined by the DELAY pin as it goes through a second cycle (TD3). During TD3, the processor VID pins settle to the required VID code. When TD3 is over, the ADP3192 soft starts either up or down to the final VID voltage (TD4). After TD4 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is completed, a third ramp on the DELAY pin sets the PWRGD blanking (TD5). TD1 TD3 TD2 TD5 50µs TD4 SS 5V SUPPLY VTT I/O (ADP3192 EN) DELAY VCC_CORE VR READY (ADP3192 PWRGD) CPU VID INPUTS VID INVALID VID VALID VBOOT (1.1V) VBOOT (1.1V) UVLO THRESHOLD 0.85V VVID VVID 1V VDELAY(TH) (1.7V) Figure 7. System Start-Up Sequence PHASE DETECTION SEQUENCE During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3192 operates as a 4-phase PWM controller. Connecting the PWM4 pin to VCC programs 3-phase operation and connecting the PWM4 and PWM3 pins to VCC programs 2-phase operation. Prior to soft start, while EN is low, the PWM3 and PWM4 pins sink approximately 100 μA. An internal comparator checks each pin’s voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval that occurs during the first five clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 μA current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 μA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases. |
Número de pieza similar - ADP3192 |
|
Descripción similar - ADP3192 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |