Philips Semiconductors

Product specification

74F50729

Synchronizing dual D-type flip-flop with edge-triggered

set and reset and metastable immune characteristics

2

1990 Sep 14

853-1390 00420

FEATURES

applications

edge–triggered flip–flop

DESCRIPTION

The 74F50729 is a dual positive edge–triggered D–type featuring

individual data, clock, set and reset inputs; also true and

complementary outputs.

The 74F50729 is designed so that the outputs can never display a

metastable state due to setup and hold time violations. If setup time

and hold time are violated the propagation delays may be extended

beyond the specifications but the outputs will not glitch or display a

metastable state. Typical metastability parameters for the 74F50729

are:

of the rate at which a latch in a metastable state resolves that

propensity of a latch to enter a metastable state.

Set (SDn) and reset (RDn) are asynchronous positive–edge

triggered inputs and operate independently of the clock (CPn) input.

Data must be stable just one setup time prior to the low–to–high

transition of the clock for guaranteed propagation delays.

Clock triggering occurs at a voltage level and is not directly related

to the transition time of the positive–going pulse. Following the hold

time interval, data at the Dn input may be changed without affecting

the levels of the output.

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

SD1

Q1

Q1

CP1

RD1

D1

RD0

D0

Q0

CP0

SD0

Q0

SF00611

TYPE

TYPICAL SUPPLY

CURRENT (TOTAL)

74F50729

120 MHz

19mA

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

INDUSTRIAL RANGE

DESCRIPTION

PKG DWG #

14–pin plastic DIP

N74F50729N

I74F50729N

SOT27-1

14–pin plastic SO

N74F50729D

I74F50729D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/

LOW

LOAD VALUE HIGH/

LOW

D0, D1

Data inputs

1.0/0.417

20

µA/250µA

CP0, CP1

Clock inputs (active rising edge)

1.0/1.0

20

µA/20µA

SD0, SD1

Set inputs (active rising edge)

1.0/1.0

20

µA/20µA

RD0, RD1

Reset inputs (active rising edge)

1.0/1.0

20

µA/20µA

Q0, Q1, Q0, Q1

Data outputs

750/33

15mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.