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WV3HG264M72EEU806PD4ISG Datasheet(PDF) 8 Page - White Electronic Designs Corporation

No. de pieza WV3HG264M72EEU806PD4ISG
Descripción Electrónicos  1GB - 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL
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Fabricante Electrónico  WEDC [White Electronic Designs Corporation]
Página de inicio  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

WV3HG264M72EEU806PD4ISG Datasheet(HTML) 8 Page - White Electronic Designs Corporation

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WV3HG264M72EEU-PD4
April 2006
Rev. 2
ADVANCED
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ACTIVE to ACTIVE (same bank) command
tRC
TBD
TBD
55
55
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
TBD
TBD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
TBD
15
15
15
ns
Four Bank Activate period
tFAW
TBD
TBD
37.5
37.5
37.5
37.5
37.5
37.5
ns
ACTIVE to PRECHARGE command
tRAS
TBD
TBD
45
70,000
45
70,000
45
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
TBD
7.5
7.5
7.5
ns
Write recovery time
tWR
TBD
TBD
15
15
15
ns
Auto precharge write recovery + precharge
time
tDAL
TBD
TBD
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
TBD
7.5
7.5
10
ns
PRECHARGE command period
tRP
TBD
TBD
15
15
15
ns
PRECHARGE ALL command period
tRPA
TBD
TBD
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
TBD
TBD
222
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
TBD
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
ns
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
TBD
TBD
105
70,000
105
70,000
105
70,000
ns
Average periodic refresh interval
tREFI
TBD
TBD
7.8
7.8
7.8
µs
Exit self refresh to non-READ command
tXSNR
TBD
TBD
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
TBD
TBD
200
200
200
tCK
Exit self refresh timing reference
tISXR
TBD
TBD
tIS
tIS
tIS
ps
ODT turn-on delay
tAOND
TBD
TBD
222222
tCK
ODT turn-on
tAON
TBD
TBD
tAC
(MIN)
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
TBD
TBD
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
TBD
tAC
(MIN) +
2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN) +
2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN) +
2000
2 x tCK
+ tAC
(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
TBD
tAC
(MIN) +
2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN) +
2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN) +
2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
ps
ODT to power-down entry latency
tANPD
TBD
TBD
333
tCK
ODT power-down exit latency
tAXPD
TBD
TBD
888
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
TBD
TBD
222
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
TBD
TBD
7 - AL
6 - AL
6 - AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
TBD
TBD
222
tCK
CKE minimum high/low time
tCKE
TBD
TBD
333
tCK
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.


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