December 1990

2

Philips Semiconductors

Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state

74HC/HCT173

FEATURES

• Gated input enable for hold (do nothing) mode

• Gated output enable control

• Edge-triggered D-type register

• Asynchronous master reset

• Output capability: bus driver

GENERAL DESCRIPTION

The 74HC/HCT173 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with

and master reset (MR).

synchronously with the LOW-to-HIGH clock (CP)

set-up time prior to the LOW-to-HIGH clock transition, the

register will retain the previous data. Data inputs and clock

enable inputs are fully edge-triggered and must be stable

only one set-up time prior to the LOW-to-HIGH clock

transition.

The master reset input (MR) is an active HIGH

asynchronous input. When MR is HIGH, all four flip-flops

are reset (cleared) independently of any other input

condition.

The 3-state output buffers are controlled by a 2-input NOR

outputs are forced to a high impedance OFF-state. The

3-state output buffers are completely independent of the

clock and reset operations.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

17

13

17

17

ns

ns

maximum clock frequency

88

88

MHz

input capacitance

3.5

3.5

pF

power dissipation

capacitance per flip-flop

notes 1 and 2

20

20

pF