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STE2001DIE2 Datasheet(Hoja de datos) 7 Page - STMicroelectronics

No. de Pieza. STE2001DIE2
Descripción  65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
Descarga  36 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STE2001
CIRCUIT DESCRIPTION
Supplies Voltages and Grounds
VDD2 and VDD3 are supply voltages to the internal voltage generator (see below). They must be externally connected.
If the internal voltage generator is not used, these should be connected to VDD1 pad. VDD1 supplies the rest of the IC.
This supply voltage could be different form VDD2 and VDD3.VDD1 must be lower than VDD2,3 + 0.5V.
Internal Supply Voltage Generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply volt-
age generation. The multiplyin g factor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplica tion’
Command. The output voltage (VLCDOUT) is tightly controlled through the VLCDSENSE pad. For this voltage, four dif-
ferent temperature coefficient s(TC, rate of change with temperature) can be programmed using the bits TC1 and TC0.
This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the V
LCDIN
and VLCDOUT pads must be connected together. An external supply could be connected to VLCDIN to supply the LCD
without using the internal generator. In such event the VLDCOUT and VLCDSENSE must be connected to GND and the
internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the Displa y System.
When used the OSC pad must be connectedto VDD1 pad. An external oscilla torcould be used and fed into the OSC pin.
Display Data RAM
The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to
Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accom-
plished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal)
and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX = 0 and V = 0), having the column with address X = 0 located on the left of the memory map.
The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is mod-
ified to jump to next row. X restarts from X = 0 (Fig.2).
• Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next colum n and Y restarting from Y = 0. (Fig. 3).
• Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory
map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer
is modified to jump to next row. X restarts from X = 0 (fig. 4).
• Mirrored Vertical (MX =1 and V = 1), having the column with address X = 0 located on the right of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next colum n and Y restarting from Y = 0. (Fig. 5).
After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0). Data
bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7).
Mux 65 Mode
The STE2001 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis
is enabled setting to a logic one the MY bit. This function is achieve d reading the matrix from physical row 63 to 0,
since the relation between the physical memory rows and the output row drivers is only dependent on the memory
reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of
the memory map. It is only related to the visualizatio nprocess (Fig. 8 & Fig. 9).
It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axis of
each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the
Interface Pads are located), setting the TRS bit to a logic one, and on the Row Pads located on the other edge, setting
the BRS bit to a logic one.
Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic
data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)




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