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UPD703101A Datasheet(PDF) 97 Page - NEC |
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UPD703101A Datasheet(HTML) 97 Page - NEC |
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97 / 185 page  CHAPTER 5 INSTRUCTIONS User’s Manual U12197EJ6V0UM 97 SAR Shift Arithmetic Right Instruction format (1) SAR reg1, reg2 (2) SAR imm5, reg2 Operation (1) GR [reg2] ← GR [reg2] arithmetically shift right by GR [reg1] (2) GR [reg2] ← GR [reg2] arithmetically shift right by zero-extend Format (1) Format IX (2) Format II Opcode 15 0 31 16 (1) rrrrr111111RRRRR 0000000010100000 15 0 (2) rrrrr010101iiiii Flag CY 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. OV 0 S 1 if the result of an operation is negative; otherwise, 0. Z 1 if the result of an operation is 0; otherwise, 0. SAT – Instruction (1) SAR Shift Arithmetic Right by Register (2) SAR Shift Arithmetic Right by Immediate (5-bit) Explanation (1) Arithmetically shifts the word data of general-purpose register reg2 to the right by ‘n’ positions, where ‘n’ is a value from 0 to +31, specified by the lower 5 bits of general- purpose register reg1 (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result in general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. The data of general-purpose register reg1 is not affected. (2) Arithmetically shifts the word data of general-purpose register reg2 to the right by ‘n’ positions, where ‘n’ is a value from 0 to +31, specified by the 5-bit immediate data, zero- extended to word length (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result in general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. |
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