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ADN2860 Datasheet(PDF) 5 Page - Analog Devices |
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ADN2860 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 20 page  ADN2860 Rev. A | Page 5 of 20 ELECTRICAL CHARACTERISTICS Single Supply: VDD = 3 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted. Dual Supply: VDD = +2.25 V or +2.75 V, VSS = −2.25 V or −2.75 V, and −40°C < TA < +85°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS 2, 3 Bandwidth −3 dB BW VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ. 125/12 kHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz. 0.05 % VW Settling Time tS VA = VDD, VB = 0 V, VW = 0.50% error band, code = 0x000 to 0x100, RAB = 25 kΩ/250 kΩ. 4/36 µs Resistor Noise Spectral Density eN_WB RAB = 25 kΩ/250 kΩ, TA = 25°C. 14/45 nV√Hz Digital Crosstalk CT VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change. −80 dB Analog Crosstalk CAT Signal input at A0 and measure output at W1, f = 1 kHz. −72 dB INTERFACE TIMING CHARACTERISTICS (Apply to All Parts)4, 5 SCL Clock Frequency fSCL 400 kHz tBUF Bus Free Time between Stop and Start t1 1.3 µs tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is generated. 600 ns tLOW Low Period of SCL Clock t3 1.3 µs tHIGH High Period of SCL Clock t4 0.6 50 µs tSU;STA Setup Time for Start Condition t5 600 ns tHD;DAT Data Hold Time t6 900 ns tSU;DAT Data Setup Time t7 100 ns tR Rise Time of Both SDA and SCL Signals t8 300 ns tF Fall Time of Both SDA and SCL Signals t9 300 ns tSU;STO Setup Time for Stop Condition t10 600 ns EEMEM Data Storing Time tEEMEM_STORE 26 ms EEMEM Data Restoring Time at Power-On tEEMEM_RESTORE1 360 µs EEMEM Data Restoring Time on Restore tEEMEM_RESTORE2 360 µs Command or Reset Operation EEMEM Data Rewritable Time tEEMEM_REWRITE 540 µs FLASH/EE MEMORY RELIABILITY Endurance6 100 kcycles Data Retention7 55°C. 100 years 1 Typical represents average readings at 25°C, VDD = 5 V. 2 All dynamic characteristics use VDD = 5 V. 3 Guaranteed by design and not subject to production test. 4 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 5 See Figure 2 for the location of measured values. 6 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles. 7 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. |
Número de pieza similar - ADN2860 |
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Descripción similar - ADN2860 |
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