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UPD703102A Datasheet(PDF) 36 Page - NEC |
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UPD703102A Datasheet(HTML) 36 Page - NEC |
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36 / 185 page  CHAPTER 4 ADDRESS SPACE User’s Manual U12197EJ6V0UM 36 4.2.2 Operand address When an instruction is executed, the register or memory area to be accessed is specified in one of the following four addressing modes. (1) Register addressing The general-purpose register (or system register) specified in the general-purpose register specification field is accessed as the operand. This addressing mode applies to instructions using the operand format reg1, reg2, or regID. (2) Immediate addressing The 5-bit or 16-bit data for manipulation is contained directly in the instruction. This addressing mode applies to instructions using the operand format imm5, imm16, vector, or cccc. Remark vector: An operand that is 5-bit immediate data that specifies the trap vector (00H to 1FH), and is used by the TRAP instruction. cccc: An operand consisting of 4-bit data used by the SETF and CMOV instructions to specify the condition code. Assigned as part of the instruction code as 5-bit immediate data by appending a 1-bit 0 above the highest bit. (3) Based addressing The following two types of based addressing are supported. (a) Type 1 The address of the data memory location to be accessed is determined by adding the value in the specified general-purpose register to the 16-bit displacement value contained in the instruction. This addressing mode applies to instructions using the operand format disp16 [reg1]. Figure 4-5. Based Addressing (Type 1) 31 reg1 0 Memory to be manipulated 31 16 15 disp16 0 Sign extension |
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