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FIN224AC Datasheet(Hoja de datos) 6 Page - Fairchild Semiconductor

No. de Pieza. FIN224AC
Descripción  USerDes 22-Bit Bi-Directional Serializer/Deserializer
Descarga  23 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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©2006 Fairchild Semiconductor Corporation
6
www.fairchildsemi.com
FIN224AC Rev. 1.0.7
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially
identically in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the
STROBE signal or not. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF
must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower fre-
quency than STROBE.
The PLL must receive a stable CKREF signal to achieve lock prior to any valid
data being sent. The CKREF signal can be used as the data STROBE signal
provided that data can be ignored during the PLL lock phase.
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and then serial-
ized. The serialized data stream is synchronized and sent source synchronously
with a bit clock with an embedded word boundary. When operating in this mode,
the internal deserializer circuitry is disabled, including the serial clock, serial data
input buffers, the bi-directional parallel outputs, and the CKP word clock. The
CKP word clock is driven HIGH.
Figure 5. Serializer Timing Diagram (CKREF = STROBE)
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data cor-
rectly. The actual serial transfer rate remains at 13 times the CKREF frequency.
A data bit value of zero is sent when no valid data is present in the serial bit
stream. The operation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs to run at depends upon the
stability of the CKREF and STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the max frequency of the spread spec-
trum clock should be used in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has significant cycle-to-cycle
variation, the maximum cycle-to-cycle time needs to be factored into the selec-
tion of the CKREF frequency.
Figure 6. Serializer Timing Diagram (CKREF does not equal STROBE)
WORD n-1
WORD n-2
WORD n-1
WORD n
DPI[1:24]
CKREF/STROBE
DSO
CKS0
b24 b25 b26
b1
b2
b3
b4
b1
b2
b3
b4
B5
b22 b23 b24 b25 b26
WORD n+1
WORD n
WORD n-1
WORD n-1
WORD n
No Data
No Data
CKREF
DP[1:24]
DSO
CKS0
STROBE
b1 b2 b3
b1 b2 b3
b4 b5 b6 b7
b22 b23 b24 b25 b26
WORD n+1
WORD n
Serializer Operation: (Figure 5)
MODE 1 or MODE 2,
DIRI = 1,
CKREF = STROBE
Serializer Operation: (Figure 6),
DIRI = 1,
CKREF does not = STROBE




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