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STE2004 Datasheet(PDF) 27 Page - STMicroelectronics |
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STE2004 Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 66 page  27/66 STE2004 out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac- knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2004 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is nec- essary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2004 is able to detect the special se- quence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode with- out detecting the master code. Figure 31. Bit transfer and START,STOP conditions definition Figure 32. Acknowledgment on the I2C-bus 4.1.1 Communication Protocol The STE2004 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1. To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W). All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED START CONDITION STOP CONDITION CLOCK DATA LR0069 START CLOCK PULSE FOR ACKNOWLEDGEMENT DATA OUTPUT BY RECEIVER SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER LR0070 1 MSB LSB 28 9 |
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