Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADSP-2187NBCA-320 Datasheet(PDF) 5 Page - Analog Devices |
|
ADSP-2187NBCA-320 Datasheet(HTML) 5 Page - Analog Devices |
5 / 45 page –5– REV. 0 ADSP-218xN Series Table 2. Common-Mode Pins Pin Name # of Pins I/O Function RESET 1 I Processor Reset Input BR 1I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1O Program Memory Select Output IOMS 1O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2 1 I Edge- or Level-Sensitive Interrupt Request1 PF7 I/O Programmable I/O pin IRQL1 1 I Level-Sensitive Interrupt Requests 1 PF6 I/O Programmable I/O Pin IRQL0 1 I Level-Sensitive Interrupt Requests 1 PF5 I/O Programmable I/O Pin IRQE 1 I Edge-Sensitive Interrupt Requests 1 PF4 I/O Programmable I/O Pin Mode D 1 I Mode Select Input—Checked Only During RESET PF3 I/O Programmable I/O Pin During Normal Operation Mode C 1 I Mode Select Input—Checked Only During RESET PF2 I/O Programmable I/O Pin During Normal Operation Mode B 1 I Mode Select Input—Checked Only During RESET PF1 I/O Programmable I/O Pin During Normal Operation Mode A 1 I Mode Select Input—Checked Only During RESET PF0 I/O Programmable I/O Pin During Normal Operation CLKIN 1 I Clock Input XTAL 1 O Quartz Crystal Output CLKOUT 1 O Processor Clock Output SPORT0 5 I/O Serial Port I/O Pins SPORT1 5 I/O Serial Port I/O Pins IRQ1 – 0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO2 PWD 1 I Power-Down Control Input PWDACK 1 O Power-Down Acknowledge Control Output FL0, FL1, FL2 3 O Output Flags V DDINT 2I Internal V DD (1.8 V) Power (LQFP) V DDEXT 4I External V DD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP) GND 10 I Ground (LQFP) V DDINT 4I Internal V DD (1.8 V) Power (Mini-BGA) V DDEXT 7I External V DD (1.8 V, 2.5 V, or 3.3 V) Power (Mini- BGA) GND 20 I Ground (Mini-BGA) EZ-Port 9 I/O For Emulation Use 1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2SPORT configuration determined by the DSP System Control Register. Software configurable. |
Número de pieza similar - ADSP-2187NBCA-320 |
|
Descripción similar - ADSP-2187NBCA-320 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |