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TPS79928DDCRG4 Datasheet(PDF) 11 Page - Texas Instruments

No. de pieza TPS79928DDCRG4
Descripción Electrónicos  200mA, Low Quiescent Current, Ultra-Low Noise, High PSRR Low Dropout Linear Regulator
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TPS79928DDCRG4 Datasheet(HTML) 11 Page - Texas Instruments

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Startup
V =xV
N
OUT
10.5 V
m
RMS
V
(1)
Board Layout Recommendations to Improve
Transient Response
Internal Current Limit
Under-Voltage Lock-Out (UVLO)
Shutdown
Minimum Load
Dropout Voltage
TPS799xx
SBVS056G – JANUARY 2005 – REVISED AUGUST 2006
Noise can be referred to the feedback point (FB pin)
such
that
with
CNR = 0.01µF total noise is
Fixed voltage versions of the TPS799xx use a
approximately given by Equation 1:
quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see Functional Block
Diagrams, Figure 1). This allows the combination of
very low output noise and fast start-up times. The
The TPS79901 adjustable version does not have the
NR pin is high impedance so a low leakage CNR
noise-reduction pin available, so ultra-low noise
capacitor must be used; most ceramic capacitors are
operation is not possible. Noise can be minimized
appropriate in this configuration.
according to the above recommendations.
Note that for fastest startup, VIN should be applied
first, then the enable pin (EN) driven high. If EN is
PSRR and Noise Performance
tied to IN, startup will be somewhat slower. Refer to
Figure
25
and
Figure
26
in
the
Typical
To improve ac performance such as PSRR, output
Characteristics section. The quick-start switch is
noise, and transient response, it is recommended
closed for approximately 135
µs. To ensure that C
NR
that the board be designed with separate ground
is fully charged during the quick-start time, a 0.01
µF
planes for VIN and VOUT, with each ground plane
or smaller capacitor should be used.
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
As with any regulator, increasing the size of the
output
capacitor
will
reduce
over/undershoot
magnitude but increase duration of the transient
response. In the adjustable version, adding CFB
The TPS799xx internal current limit helps protect the
between OUT and FB will improve stability and
regulator during fault conditions. During current limit,
transient response. The transient response of the
the output will source a fixed amount of current that
TPS799xx is enhanced by an active pull-down that
is largely independent of output voltage. For reliable
engages
when
the
output
overshoots
by
operation, the device should not be operated in
approximately 5% or more when the device is
current limit for extended periods of time.
enabled.
When
enabled,
the
pull-down
device
behaves like a 350
Ω resistor to ground.
The PMOS pass element in the TPS799xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
The TPS799xx utilizes an under-voltage lock-out
operation is anticipated, external limiting may be
circuit to keep the output shut off until internal
appropriate.
circuitry is operating properly. The UVLO circuit has
a de-glitch feature so that it will typically ignore
undershoot transients on the input if they are less
than 50
µs duration.
The enable pin (EN) is active high and is compatible
with standard and low voltage TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
The TPS799xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
minimum load of 500
µA is required. Below 500µA at
junction temperatures near +125
°C, the output can
The TPS799xx uses a PMOS pass transistor to
drift up enough to cause the output pull-down to turn
achieve low dropout. When (VIN – VOUT) is less than
on. The output pull-down will limit voltage drift to 5%
the dropout voltage (VDO), the PMOS pass device is
typically but ground current could increase by
in
its
linear
region
of
operation
and
the
approximately 50
µA. In typical applications, the
input-to-output resistance is the RDS, ON of the PMOS
junction cannot reach high temperatures at light
pass element. Because the PMOS device behaves
loads since there is no appreciable dissipated power.
like a resistor in dropout, VDO will approximately
The specified ground current would then be valid at
scale with output current.
no load in most applications.
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 18 through
Figure 20 in the Typical Characteristics section.
11
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