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ST20GP6X33S Datasheet(PDF) 1 Page - STMicroelectronics |
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ST20GP6X33S Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 123 page 1/123 ® October 2004 GPS PROCESSOR ST20-GP6 FEATURES ■ Application specific features • 12 channel GPS correlation DSP hardware, ST20 CPU (for control and position calculations) and memory on one chip • no TCXO required • RTCA-SC159 / WAAS / EGNOS supported ■ GPS performance • accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm • time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s ■ Enhanced 32-bit VL-RISC CPU - C2 core • 16/33/50 MHz processor clock • 25 MIPS at 33 MHz • fast integer/bit operations ■ 64 Kbytes on-chip SRAM ■ 128 Kbytes on-chip ROM ■ Programmable memory interface • 4 separately configurable regions • 8/16-bits wide • support for mixed memory • 2 cycle external access ■ Programmable UART (ASC) ■ Parallel I/O ■ Vectored interrupt subsystem ■ Diagnostic control unit ■ Power management • low power operation • power down modes ■ Professional toolset support • ANSI C compiler/link driver and libraries • Debugging/profiling and simulation tools ■ Technology • Static clocked 50 MHz design • 3.3 V, sub micron technology ■ 100 pin PQFP package ■ JTAG Test Access Port Figure 1. Package Table 1. Order Codes Figure 2. Block Diagram APPLICATIONS ■ Global Positioning System (GPS) receivers ■ Car navigation systems ■ Fleet management systems ■ Time reference for telecom systems Part Number Package ST20GP6X33S PQFP100 PQFP100 GPS radio 12 channel GPS Low controller power Real time clock/calendar 64K SRAM Programmable memory interface ST20-GP6 ST20 CPU Interrupt controller Serial communications Parallel input/output Diagnostic control unit ... 16 2 UART (ASC) hardware DSP 128K optional mask ROM Test access port Rev. 2 |
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