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DS42BR400 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
No. de Pieza. DS42BR400
Descripción  Quad Transceiver with Input Equalization and Output De-Emphasis
Descarga  12 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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DS42BR400 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Pin Descriptions
Pin Name
Pin
Number
I/O
Description
DIFFERENTIAL I/O
IB_0+
IB_0−
51
52
I
Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally
connected to a reference voltage through a 50
Ω resistor.
OA_0+
OA_0−
48
49
O
Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected
to V
CC through a 50
Ω resistor.
IB_1+
IB_1−
43
42
I
Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally
connected to a reference through a 50
Ω resistor.
OA_1+
OA_1−
40
39
O
Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected
to V
CC through a 50
Ω resistor.
IB_2+
IB_2−
33
34
I
Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally
connected to a reference voltage through a 50
Ω resistor.
OA_2+
OA_2−
36
37
O
Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected
to V
CC through a 50
Ω resistor.
IB_3+
IB_3−
25
24
I
Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally
connected to a reference voltage through a 50
Ω resistor.
OA_3+
OA_3−
28
27
O
Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected
to V
CC through a 50
Ω resistor.
IA_0+
IA_0−
58
57
I
Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally
connected to a reference voltage through a 50
Ω resistor.
OB_0+
OB_0−
55
54
O
Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected
to V
CC through a 50
Ω resistor.
IA_1+
IA_1−
6
7
I
Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally
connected to a reference through a 50
Ω resistor.
OB_1+
OB_1−
3
4
O
Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected
to V
CC through a 50
Ω resistor.
IA_2+
IA_2−
10
9
I
Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally
connected to a reference voltage through a 50
Ω resistor.
OB_2+
OB_2−
13
12
O
Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected
to V
CC through a 50
Ω resistor.
IA_3+
IA_3−
18
19
I
Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally
connected to a reference voltage through a 50
Ω resistor.
OB_3+
OB_3−
21
28
O
Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected
to V
CC through a 50
Ω resistor.
CONTROL (3.3V LVCMOS)
EQA
60
I
This pin is active LOW. A logic LOW at EQA enables equalization for input channels
IA_0±, IA_1±, IA_2±, and IA_3±. By default, this pin is internally pulled high and
equalization is disabled.
EQB
16
I
This pin is active LOW. A logic LOW at EQB enables equalization for input channels
IB_0±, IB_1±, IB_2±, and IB_3±. By default, this pin is internally pulled high and
equalization is disabled.
PreA_0
PreA_1
15
1
I
PreA_0 and PreA_1 select the output de-emphasis levels (OA_0±, OA_1±, OA_2±, and
OA_3±). PreA_0 and PreA_1 are internally pulled high. Please see Table 2 for
de-emphasis levels.
PreB_0
PreB_1
31
45
I
PreB_0 and PreB_1 select the output de-emphasis levels (OB_0±, OB_1±, OB_2±, and
OB_3±). PreB_0 and PreB_1 are internally pulled high. Please see Table 2 for
de-emphasis levels.
LB0
46
I
This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0±
to OA_0±. LB0 is internally pulled high. Please see Table 1 for more information.
LB1
44
I
This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1±
to OA_1±. LB1 is internally pulled high. Please see Table 1 for more information.
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