Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

AD9980 Datasheet(PDF) 11 Page - Analog Devices

No. de pieza AD9980
Descripción Electrónicos  High Performance 8-Bit Display Interface
Download  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9980 Datasheet(HTML) 11 Page - Analog Devices

Back Button AD9980 Datasheet HTML 7Page - Analog Devices AD9980 Datasheet HTML 8Page - Analog Devices AD9980 Datasheet HTML 9Page - Analog Devices AD9980 Datasheet HTML 10Page - Analog Devices AD9980 Datasheet HTML 11Page - Analog Devices AD9980 Datasheet HTML 12Page - Analog Devices AD9980 Datasheet HTML 13Page - Analog Devices AD9980 Datasheet HTML 14Page - Analog Devices AD9980 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 44 page
background image
AD9980
Rev. 0 | Page 11 of 44
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync.
Fortunately, there is virtually always a period following Hsync,
called the ‘back porch’, where a good black reference is provided.
This is the time when clamping should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time with clamp source
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bit (Register 0x1B, Bits [7:6]).
A simpler method of clamp timing uses the AD9980’s internal
clamp timing generator. The clamp placement register
(Register 0x19) is programmed with the number of pixel
periods that should pass after the trailing edge of Hsync before
clamping starts. A second register, clamp duration, (Register
0x1A) sets the duration of the clamp. These are both 8-bit
values, providing considerable flexibility in clamp generation.
The clamp timing is referenced to the trailing edge of Hsync
because, though Hsync duration can vary widely, the back porch
(black reference) always follows Hsync. A good starting point
for establishing clamping is to set the clamp placement to 0x04
(providing 4 pixel periods for the graphics signal to stabilize
after sync) and set the clamp duration to 0x28 (giving the clamp
40 pixel periods to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within ½ LSB in 20 lines with a clamp duration of 20 pixel
periods on a 85 Hz XGA signal.
YPbPr Clamping
YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) for the
color difference signals is at the midpoint of the video signal
rather than at the bottom. The three inputs are composed of
luminance (Y) and color difference (Pb and Pr) signals. For the
color difference signals it is necessary to clamp to the midscale
range of the ADC range (128) rather than at the bottom of the
ADC range (0) while the Y channel is clamped to ground.
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
independently clamped to either midscale or ground. These bits
are located in Register 0x18, Bits [3:1]. The midscale reference
voltage is internally generated for each converter.
GAIN AND OFFSET CONTROL
The AD9980 contains three PGAs, one for each of the three
analog inputs. The range of the PGA is sufficient to accom-
modate input signals with inputs ranging from 0.5 V to 1.0 V
full scale. The gain is set in three 7-bit registers (red gain [0x05],
green gain [0x07], blue gain [0x09]). For each register, a gain
setting of 0 corresponds to the highest gain, while a gain setting
of 127 corresponds to the lowest gain. Note that increasing the
gain setting results in an image with less contrast.
The offset control shifts the analog input, resulting in a change
in brightness. Three 9-bit registers (red offset [0x0B, 0x0C],
green offset [0x0D, 0x0E], blue offset [0x0F, 0x10]) provide
independent settings for each channel. The function of the
offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
If manual offset is used, seven bits of the offset registers (for the
red channel Register 0x0B, Bits [6:0] control the absolute offset
added to the channel. The offset control provides ±63 LSBs of
adjustment range, with one LSB of offset corresponding to one
LSB of output code.
Automatic Offset
In addition to the manual offset adjustment mode, the AD9980
also includes circuitry to automatically calibrate the offset for
each channel. By monitoring the output of each ADC during
the back porch of the input signals, the AD9980 can self-adjust
to eliminate any offset errors in its own ADC channels and any
offset errors present on the incoming graphics or video signals.
To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1.
Next, the target code registers (0x0B through 0x10) must be
programmed. The values programmed into the target code
registers should be the output code desired from the AD9980
ADCs, which are generated during the back porch reference
time. For example, for RGB signals, all three registers are
normally programmed to Code 1, while for YPbPr signals the
green (Y) channel is normally programmed to Code 1 and the
blue and red channels (Pb and Pr) are normally set to 128. The
target code registers have nine bits per channel and are in twos
complement format. This allows any value between –256 and
+255 to be programmed. Although any value in this range can
be programmed, the AD9980’s offset range may not be able to
reach every value. Intended target code values range from (but
are not limited to) –40 to –1 and +1 to +40 when ground
clamping and +88 to +168 when midscale clamping. (Note that
a target code of 0 is not valid.)


Número de pieza similar - AD9980

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
AD9980 AD-AD9980_15 Datasheet
967Kb / 44P
   High Performance 8-Bit Display Interface
REV. 0
More results

Descripción similar - AD9980

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
AD9983A AD-AD9983A_15 Datasheet
916Kb / 44P
   High Performance 8-Bit Display Interface
REV. 0
AD9980 AD-AD9980_15 Datasheet
967Kb / 44P
   High Performance 8-Bit Display Interface
REV. 0
AD9983A AD-AD9983A Datasheet
784Kb / 44P
   High Performance 8-Bit Display Interface
Rev. PrA
AD9984A AD-AD9984A Datasheet
844Kb / 44P
   High Performance 10-Bit Display Interface
REV. 0
AD9981 AD-AD9981 Datasheet
972Kb / 44P
   High Performance 10-Bit Display Interface
REV. 0
AD9981 AD-AD9981_15 Datasheet
973Kb / 44P
   High Performance 10-Bit Display Interface
REV. 0
AD9984A AD-AD9984A_15 Datasheet
845Kb / 44P
   High Performance 10-Bit Display Interface
REV. 0
logo
ATMEL Corporation
TS80C51RA2 ATMEL-TS80C51RA2 Datasheet
903Kb / 74P
   High Performance 8-bit Microcontrollers
logo
OKI electronic componet...
MSM65512A OKI-MSM65512A Datasheet
189Kb / 23P
   High Performance 8-Bit Microcontroller
logo
Zilog, Inc.
Z8F0423SB005SG ZILOG-Z8F0423SB005SG Datasheet
14Mb / 245P
   High-Performance 8-Bit Microcontrollers
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com