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ADF4002BCPZ Datasheet(PDF) 6 Page - Analog Devices

No. de pieza ADF4002BCPZ
Descripción Electrónicos  Phase Detector/Frequency Synthesizer
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ADF4002BCPZ Datasheet(HTML) 6 Page - Analog Devices

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ADF4002
Rev. 0 | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RFINB
RFINA
AVDD
REFIN
VP
DVDD
ADF4002
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 3. TSSOP (Top View)
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
11 CE
4
5
RFINB
RFINA
PIN 1
INDICATOR
ADF4002
TOP VIEW
(Not to Scale)
Figure 4. LFCSP_VQ (Top View)
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP_VQ
Mnemonic
Description
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
Where RSET = 5.1 kΩ and ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter that, in turn, drives
the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the RF input.
5
4
RFINB
Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 12.
6
5
RFINA
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
7
6, 7
AVDD
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking this pin high powers up the device, depending on the status of the Power-
Down Bit F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB-first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches; the latch is selected using the control bits.
14
15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
15
16, 17
DVDD
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.


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