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ADSP-21261SKBC-150 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-21261SKBC-150 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 44 page  Rev. 0 | Page 6 of 44 | March 2006 ADSP-21261 Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21261 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction. ADSP-21261 MEMORY AND I/O INTERFACE FEATURES The ADSP-21261 adds the following architectural features to the SIMD SHARC family core: Dual-Ported On-Chip Memory The ADSP-21261 contains one megabit of internal SRAM and three megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see memory map, Figure 3). Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dual-ported memory, in com- bination with three separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a sin- gle cycle. The ADSP-21261’s SRAM can be configured as a maximum of 48K words of 32-bit data, 46K words of 16-bit data, 31.5K words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to one megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. DMA Controller The ADSP-21261’s on-chip DMA controller allows zero-over- head data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simul- taneously executing its program instructions. DMA transfers can occur between the ADSP-21261’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port), parallel data acquisition port (PDAP), or the parallel port. Eighteen channels of DMA are available on the ADSP-21261—one for the SPI, eight via the serial ports, eight via the input data port, and one via the proces- sor’s parallel port. Programs can be downloaded to the ADSP- 21261 using DMA transfers. Other DMA features include inter- rupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Digital Applications Interface (DAI) The digital applications interface provides the ability to connect various peripherals to any of the SHARC’s DAI pins (DAI_P20–1). Connections are made using the signal routing unit (SRU, shown in the block diagram on Page 1). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. The DAI also includes four serial ports, two precision clock gen- erators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-21261 core, configurable as either eight channels of I2S or serial data, or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21261’s serial ports. For complete information on using the DAI, see the ADSP-2126x SHARC DSP Peripherals Manual. Serial Ports The ADSP-21261 features four full-duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the Analog Devices AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel. Serial ports are enabled via eight programmable and simulta- neous receive or transmit pins that support up to 18 transmit or 18 receive channels of serial data when all six SPORTs are enabled, or four full-duplex TDM streams of 128 channels per frame. The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of 37.5M bit/s for a 150 MHz core. Serial port data can be auto- matically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports can work in conjunc- tion with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: • Standard DSP serial mode •Multichannel (TDM) mode •I2S mode • Left-justified sample pair mode |
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