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CS5320 Datasheet(PDF) 9 Page - Applied Micro Circuits Corporation |
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CS5320 Datasheet(HTML) 9 Page - Applied Micro Circuits Corporation |
9 / 160 page S5320 – PCI Match Maker Revision 5.03 – June 14, 2006 AMCC Confidential and Proprietary DS1656 9 Data Sheet LIST OF FIGURES Figure 1. S5320 Block Diagram ............................................................................................................................... 4 Figure 2. S5320 Pinout .......................................................................................................................................... 16 Figure 3. Mailbox Block Diagram ........................................................................................................................... 17 Figure 4. Pass-Thru Block Diagram ....................................................................................................................... 18 Figure 5. S5320 Signal Assignment ....................................................................................................................... 20 Figure 6. Vendor Identification Register ................................................................................................................. 29 Figure 7. Device Identification Register ................................................................................................................. 30 Figure 8. PCI Command Register .......................................................................................................................... 31 Figure 9. PCI Status Register ................................................................................................................................ 33 Figure 10. Revision Identification Register ............................................................................................................ 35 Figure 11. Class Code Register ............................................................................................................................. 36 Figure 12. Cache Line Size Register ..................................................................................................................... 41 Figure 13. Latency Timer Register ......................................................................................................................... 42 Figure 14. Header Type Register ........................................................................................................................... 43 Figure 15. Built-In Self-Test Register ..................................................................................................................... 44 Figure 16. Base Address Register - Memory ......................................................................................................... 46 Figure 17. Base Address Register - I/O ................................................................................................................. 47 Figure 18. Subsystem Vendor Identification Register ............................................................................................ 50 Figure 19. Subsystem Identification Register ........................................................................................................ 51 Figure 20. Expansion ROM Base Address Register .............................................................................................. 52 Figure 21. Interrupt Line Register .......................................................................................................................... 54 Figure 22. Interrupt Pin Register ............................................................................................................................ 55 Figure 23. Minimum Grant Register ....................................................................................................................... 56 Figure 24. Maximum Latency Register .................................................................................................................. 57 Figure 25. Outgoing Mailbox .................................................................................................................................. 60 Figure 26. Incoming Mailbox .................................................................................................................................. 61 Figure 27. Mailbox Empty/Full Status Register (MBEF) ......................................................................................... 62 Figure 28. Interrupt Control Status Register .......................................................................................................... 63 Figure 29. FIFO Control/Status Register ............................................................................................................... 65 Figure 30. Pass-Thru Configuration Register ........................................................................................................ 67 Figure 31. Mailbox Empty/Full Status Register ...................................................................................................... 71 Figure 32. Add-On Interrupt Control Status Register ............................................................................................. 73 Figure 33. Add-On General Control/Status Register ............................................................................................. 75 Figure 34. Pass-Thru Configuration Register ........................................................................................................ 77 Figure 35. S5320 to nvRAM Interface .................................................................................................................... 81 Figure 36. Serial Interface Definition of Start and Stop .......................................................................................... 81 Figure 37. Serial Interface Clock Data Relationship .............................................................................................. 81 |
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